695 lines
20 KiB
C
695 lines
20 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : core_riscv.h
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* Author : WCH
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* Version : V1.0.0
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* Date : 2024/07/25
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* Description : CH585 Series RISC-V Core Peripheral Access Layer Header File
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*********************************************************************************
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* Copyright (c) 2024 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#ifndef __CORE_RISCV_H__
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#define __CORE_RISCV_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* define compiler specific symbols */
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#if defined ( __CC_ARM )
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#define __ASM __asm /*!< asm keyword for ARM Compiler */
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#define __INLINE __inline /*!< inline keyword for ARM Compiler */
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#elif defined ( __ICCARM__ )
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#define __ASM __asm /*!< asm keyword for IAR Compiler */
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
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#elif defined ( __GNUC__ )
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#define __ASM __asm /*!< asm keyword for GNU Compiler */
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#define __INLINE inline /*!< inline keyword for GNU Compiler */
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#elif defined ( __TASKING__ )
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#define __ASM __asm /*!< asm keyword for TASKING Compiler */
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */
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#endif
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/* IO definitions */
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#ifdef __cplusplus
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#define __I volatile /*!< defines 'read only' permissions */
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#else
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#define __I volatile const /*!< defines 'read only' permissions */
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#endif
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#define __O volatile /*!< defines 'write only' permissions */
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#define __IO volatile /*!< defines 'read / write' permissions */
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#define RV_STATIC_INLINE static inline
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//typedef enum {SUCCESS = 0, ERROR = !SUCCESS} ErrorStatus;
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typedef enum
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{
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DISABLE = 0,
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ENABLE = !DISABLE
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} FunctionalState;
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus, ITStatus;
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/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
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typedef struct
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{
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__I uint32_t ISR[8]; // 0
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__I uint32_t IPR[8]; // 20H
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__IO uint32_t ITHRESDR; // 40H
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uint8_t RESERVED[8]; // 44H
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__I uint32_t GISR; // 4CH
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__IO uint8_t VTFIDR[4]; // 50H
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uint8_t RESERVED0[0x0C]; // 54H
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__IO uint32_t VTFADDR[4]; // 60H
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uint8_t RESERVED1[0x90]; // 70H
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__O uint32_t IENR[8]; // 100H
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uint8_t RESERVED2[0x60]; // 120H
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__O uint32_t IRER[8]; // 180H
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uint8_t RESERVED3[0x60]; // 1A0H
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__O uint32_t IPSR[8]; // 200H
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uint8_t RESERVED4[0x60]; // 220H
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__O uint32_t IPRR[8]; // 280H
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uint8_t RESERVED5[0x60]; // 2A0H
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__IO uint32_t IACTR[8]; // 300H
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uint8_t RESERVED6[0xE0]; // 320H
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__IO uint8_t IPRIOR[256]; // 400H
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uint8_t RESERVED7[0x810]; // 500H
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__IO uint32_t SCTLR; // D10H
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} PFIC_Type;
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/* memory mapped structure for SysTick */
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typedef struct
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{
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__IO uint32_t CTLR;
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__IO uint32_t SR;
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union
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{
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__IO uint32_t CNT;
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__IO uint32_t CNTL;
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};
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uint8_t RESERVED[4];
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union
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{
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__IO uint32_t CMP;
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__IO uint32_t CMPL;
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};
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uint8_t RESERVED0[4];
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} SysTick_Type;
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#define PFIC ((PFIC_Type *)0xE000E000)
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#define SysTick ((SysTick_Type *)0xE000F000)
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#define PFIC_KEY1 ((uint32_t)0xFA050000)
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#define PFIC_KEY2 ((uint32_t)0xBCAF0000)
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#define PFIC_KEY3 ((uint32_t)0xBEEF0000)
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/* ########################## define #################################### */
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#define __nop() __asm__ volatile("nop")
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#define read_csr(reg) ({unsigned long __tmp; \
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__asm__ volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; })
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#define write_csr(reg, val) ({ \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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__asm__ volatile ("csrw " #reg ", %0" :: "i"(val)); \
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else \
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__asm__ volatile ("csrw " #reg ", %0" :: "r"(val)); })
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/*********************************************************************
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* @fn __risc_v_enable_irq
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*
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* @brief recover Global Interrupt
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*
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* @return mpie and mie bit in mstatus.
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __risc_v_enable_irq(uint32_t mpie_mie)
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{
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uint32_t result;
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__asm volatile("csrrs %0, 0x800, %1" : \
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"=r"(result): "r"(mpie_mie) : "memory");
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return result;
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}
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/*********************************************************************
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* @fn __disable_irq
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*
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* @brief Disable Global Interrupt
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*
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* @return mpie and mie bit in mstatus.
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __risc_v_disable_irq(void)
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{
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uint32_t result;
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__asm volatile("csrrc %0, 0x800, %1" : \
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"=r"(result): "r"(0x88) : "memory");
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return result & 0x88;
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}
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/* ########################## PFIC functions #################################### */
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#define PFIC_EnableAllIRQ() {write_csr(0x800, 0x88);__nop();__nop();}
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#define PFIC_DisableAllIRQ() {write_csr(0x800, 0x80);__nop();__nop();}
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/*******************************************************************************
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* @fn PFIC_EnableIRQ
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*
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* @brief Enable Interrupt
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*
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* @param IRQn - Interrupt Numbers
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_EnableIRQ(IRQn_Type IRQn)
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{
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PFIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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}
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/*******************************************************************************
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* @fn PFIC_DisableIRQ
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*
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* @brief Disable Interrupt
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*
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* @param IRQn - Interrupt Numbers
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_DisableIRQ(IRQn_Type IRQn)
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{
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PFIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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__nop();
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__nop();
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}
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/*******************************************************************************
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* @fn PFIC_GetStatusIRQ
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*
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* @brief Get Interrupt Enable State
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return 1: Interrupt Enable
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* 0: Interrupt Disable
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t PFIC_GetStatusIRQ(IRQn_Type IRQn)
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{
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return ((uint32_t)((PFIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
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}
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/*******************************************************************************
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* @fn PFIC_GetPendingIRQ
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*
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* @brief Get Interrupt Pending State
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return 1: Interrupt Pending Enable
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* 0: Interrupt Pending Disable
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t PFIC_GetPendingIRQ(IRQn_Type IRQn)
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{
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return ((uint32_t)((PFIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
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}
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/*******************************************************************************
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* @fn PFIC_SetPendingIRQ
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*
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* @brief Set Interrupt Pending
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*
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* @param IRQn - Interrupt Numbers
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_SetPendingIRQ(IRQn_Type IRQn)
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{
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PFIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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}
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/*******************************************************************************
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* @fn PFIC_ClearPendingIRQ
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*
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* @brief Clear Interrupt Pending
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*
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* @param IRQn - Interrupt Numbers
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_ClearPendingIRQ(IRQn_Type IRQn)
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{
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PFIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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}
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/*******************************************************************************
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* @fn PFIC_GetActive
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*
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* @brief Get Interrupt Active State
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return 1: Interrupt Active
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* 0: Interrupt No Active.
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t PFIC_GetActive(IRQn_Type IRQn)
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{
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return ((uint32_t)((PFIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
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}
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/*******************************************************************************
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* @fn PFIC_SetPriority
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*
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* @brief Set Interrupt Priority
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*
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* @param IRQn - Interrupt Numbers
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* @param priority - bit7: pre-emption priority
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
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{
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PFIC->IPRIOR[(uint32_t)(IRQn)] = priority ? 0x80 : 0;
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}
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/*********************************************************************
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* @fn SetVTFIRQ
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*
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* @brief Set VTF Interrupt
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*
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* @param addr - VTF interrupt service function base address.
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* IRQn - Interrupt Numbers
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* num - VTF Interrupt Numbers
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* NewState - DISABLE or ENABLE
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*
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* @return none
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
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{
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if (num > 3) return ;
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if (NewState != DISABLE)
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{
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PFIC->VTFIDR[num] = IRQn;
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PFIC->VTFADDR[num] = ((addr & 0xFFFFFFFE) | 0x1);
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}
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else
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{
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PFIC->VTFIDR[num] = IRQn;
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PFIC->VTFADDR[num] = ((addr & 0xFFFFFFFE) & (~0x1));
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}
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}
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/*********************************************************************
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* @fn _SEV
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*
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* @brief Set Event
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*
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* @return none
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void _SEV(void)
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{
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PFIC->SCTLR |= (1 << 3) | (1 << 5);
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}
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/*********************************************************************
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* @fn _WFE
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*
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* @brief Wait for Events
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*
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* @return none
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void _WFE(void)
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{
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PFIC->SCTLR |= (1 << 3);
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asm volatile("wfi");
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}
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/*********************************************************************
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* @fn __WFE
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*
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* @brief Wait for Events
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*
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* @return None
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void __WFE(void)
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{
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_SEV();
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_WFE();
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_WFE();
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}
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/*********************************************************************
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* @fn __WFI
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*
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* @brief Wait for Interrupt
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void __WFI(void)
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{
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PFIC->SCTLR &= ~(1 << 3); // wfi
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__asm__ volatile("wfi");
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}
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/*********************************************************************
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* @fn PFIC_SystemReset
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*
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* @brief Initiate a system reset request
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void PFIC_SystemReset(void)
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{
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PFIC->SCTLR = 0x80000000;
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}
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/*********************************************************************
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* @fn __get_MSTATUS
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*
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* @brief Return the Machine Status Register
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*
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* @return mstatus value
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_MSTATUS(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mstatus" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MSTATUS
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*
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* @brief Set the Machine Status Register
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*
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* @param value - set mstatus value
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*
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* @return none
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void __set_MSTATUS(uint32_t value)
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{
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__ASM volatile("csrw mstatus, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MISA
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*
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* @brief Return the Machine ISA Register
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*
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* @return misa value
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_MISA(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "misa" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MISA
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*
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* @brief Set the Machine ISA Register
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*
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* @param value - set misa value
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*
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* @return none
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void __set_MISA(uint32_t value)
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{
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__ASM volatile("csrw misa, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MTVEC
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*
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* @brief Return the Machine Trap-Vector Base-Address Register
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*
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* @return mtvec value
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_MTVEC(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mtvec" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MTVEC
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*
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* @brief Set the Machine Trap-Vector Base-Address Register
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*
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* @param value - set mtvec value
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*
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* @return none
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void __set_MTVEC(uint32_t value)
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{
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__ASM volatile("csrw mtvec, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MSCRATCH
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*
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* @brief Return the Machine Seratch Register
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*
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* @return mscratch value
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_MSCRATCH(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mscratch" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MSCRATCH
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*
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* @brief Set the Machine Seratch Register
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*
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* @param value - set mscratch value
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*
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* @return none
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void __set_MSCRATCH(uint32_t value)
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{
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__ASM volatile("csrw mscratch, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MEPC
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*
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* @brief Return the Machine Exception Program Register
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*
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* @return mepc value
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_MEPC(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mepc" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MEPC
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*
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* @brief Set the Machine Exception Program Register
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*
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* @return mepc value
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void __set_MEPC(uint32_t value)
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{
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__ASM volatile("csrw mepc, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MCAUSE
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*
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* @brief Return the Machine Cause Register
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*
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* @return mcause value
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_MCAUSE(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mcause" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MEPC
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*
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* @brief Set the Machine Cause Register
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*
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* @return mcause value
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE void __set_MCAUSE(uint32_t value)
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{
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__ASM volatile("csrw mcause, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MTVAL
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*
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* @brief Return the Machine Trap Value Register
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*
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* @return mtval value
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*/
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__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_MTVAL(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mtval" : "=r"(result));
|
|
return (result);
|
|
}
|
|
|
|
/*********************************************************************
|
|
* @fn __set_MTVAL
|
|
*
|
|
* @brief Set the Machine Trap Value Register
|
|
*
|
|
* @return mtval value
|
|
*/
|
|
__attribute__((always_inline)) RV_STATIC_INLINE void __set_MTVAL(uint32_t value)
|
|
{
|
|
__ASM volatile("csrw mtval, %0" : : "r"(value));
|
|
}
|
|
|
|
/*********************************************************************
|
|
* @fn __get_MVENDORID
|
|
*
|
|
* @brief Return Vendor ID Register
|
|
*
|
|
* @return mvendorid value
|
|
*/
|
|
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_MVENDORID(void)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile("csrr %0," "mvendorid" : "=r"(result));
|
|
return (result);
|
|
}
|
|
|
|
/*********************************************************************
|
|
* @fn __get_MARCHID
|
|
*
|
|
* @brief Return Machine Architecture ID Register
|
|
*
|
|
* @return marchid value
|
|
*/
|
|
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_MARCHID(void)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile("csrr %0," "marchid" : "=r"(result));
|
|
return (result);
|
|
}
|
|
|
|
/*********************************************************************
|
|
* @fn __get_MIMPID
|
|
*
|
|
* @brief Return Machine Implementation ID Register
|
|
*
|
|
* @return mimpid value
|
|
*/
|
|
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_MIMPID(void)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile("csrr %0," "mimpid" : "=r"(result));
|
|
return (result);
|
|
}
|
|
|
|
/*********************************************************************
|
|
* @fn __get_MHARTID
|
|
*
|
|
* @brief Return Hart ID Register
|
|
*
|
|
* @return mhartid value
|
|
*/
|
|
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_MHARTID(void)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile("csrr %0," "mhartid" : "=r"(result));
|
|
return (result);
|
|
}
|
|
|
|
/*********************************************************************
|
|
* @fn __get_SP
|
|
*
|
|
* @brief Return SP Register
|
|
*
|
|
* @return SP value
|
|
*/
|
|
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __get_SP(void)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile("mv %0," "sp" : "=r"(result) :);
|
|
return (result);
|
|
}
|
|
|
|
/*********************************************************************
|
|
* @fn __MCPY
|
|
*
|
|
* @brief fast memory copy asm instruction.
|
|
* @details copy memory from start to dst, copy length is (end - start).
|
|
*
|
|
*
|
|
* @return None.
|
|
*/
|
|
__attribute__((always_inline)) RV_STATIC_INLINE void __MCPY(void *dst, void *start, void *end)
|
|
{
|
|
__asm volatile("mcpy %2, %0, %1" : \
|
|
"+r"(start), "+r"(dst) : "r"(end) : "memory");
|
|
}
|
|
|
|
#define SysTick_SR_SWIE (1 << 31)
|
|
#define SysTick_SR_CNTIF (1 << 0)
|
|
|
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFFF)
|
|
#define SysTick_CTLR_MODE (1 << 4)
|
|
#define SysTick_CTLR_STRE (1 << 3)
|
|
#define SysTick_CTLR_STCLK (1 << 2)
|
|
#define SysTick_CTLR_STIE (1 << 1)
|
|
#define SysTick_CTLR_STE (1 << 0)
|
|
|
|
|
|
RV_STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)
|
|
return (1); /* Reload value impossible */
|
|
|
|
SysTick->CNTL = 0;
|
|
SysTick->CMP = ticks - 1; /* set reload register */
|
|
PFIC_EnableIRQ(SysTick_IRQn);
|
|
SysTick->CTLR = SysTick_CTLR_STRE |
|
|
SysTick_CTLR_STCLK |
|
|
SysTick_CTLR_STIE |
|
|
SysTick_CTLR_STE; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0); /* Function successful */
|
|
}
|
|
|
|
RV_STATIC_INLINE uint32_t __SysTick_Config(uint32_t ticks)
|
|
{
|
|
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)
|
|
return (1); /* Reload value impossible */
|
|
|
|
SysTick->CNTL = 0;
|
|
SysTick->CMP = ticks - 1; /* set reload register */
|
|
SysTick->CTLR = SysTick_CTLR_STRE |
|
|
SysTick_CTLR_STCLK |
|
|
SysTick_CTLR_STIE |
|
|
SysTick_CTLR_STE; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0); /* Function successful */
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __CORE_RV3A_H__ */
|