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CIU32_L051_M307R
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CIU32_L051_M307R/Peripheral/CIU32L051_Lib/Include/ciu32l051_std_adc.h

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移植了RTThread和RTT打印，并完成了串口的DMA中断发送，和串口空闲中断+DMA接收，测试通过
2024-08-22 16:24:54 +08:00
/************************************************************************************************/
/**
* @file ciu32l051_std_adc.h
* @author MCU Ecosystem Development Team
* @brief ADC STD<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD>ṩADC<EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>STD<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Լ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ķ<EFBFBD><EFBFBD>塣
*
*
**************************************************************************************************
* @attention
* Copyright (c) CEC Huada Electronic Design Co.,Ltd. All rights reserved.
*
**************************************************************************************************
*/
/* <20><><EFBFBD><EFBFBD>ͷ<EFBFBD>ļ<EFBFBD><C4BC>ظ<EFBFBD><D8B8><EFBFBD><EFBFBD><EFBFBD> */
#ifndef CIU32L051_STD_ADC_H
#define CIU32L051_STD_ADC_H
/************************************************************************************************/
/**
* @addtogroup CIU32L051_STD_Driver
* @{
*/
/**
* @defgroup ADC ADC
* @brief ģ<EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>STD<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @{
*/
/************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------includes--------------------------------------------*/
#include "ciu32l051_std_common.h"
/*-----------------------------------------type define------------------------------------------*/
/************************************************************************************************/
/**
* @defgroup ADC_Types ADC Types
* @brief ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ͷ<EFBFBD><EFBFBD><EFBFBD>
* @{
*/
/************************************************************************************************/
/**
* @brief ADC<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD>嶨<EFBFBD><EFBFBD>
*/
typedef struct
{
uint32_t clock_src; /**< ʱ<><CAB1>Դ<EFBFBD><D4B4>ͬ<EFBFBD><CDAC>ʱ<EFBFBD><CAB1>PCLK<4C><4B><EFBFBD>첽ʱ<ECB2BD><CAB1>RCH16<31><36>SYSCLK<4C><4B><EFBFBD><EFBFBD>Ƶ
@arg ADC_SYNC_CLK_PCLK_DIV1 ... */
uint32_t clock_presc; /**< <20>첽ʱ<ECB2BD>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>
@arg ADC_ASYNC_CLK_DIV1 ... */
uint32_t trigger_edge; /**< <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD>ͼ<EFBFBD><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
@arg ADC_TRIG_SW ... */
uint32_t trigger_source; /**< ת<><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դѡ<D4B4>񣬵<EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ⲿ<EFBFBD><E2B2BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ
@arg ADC_EXTRIG_EXTI11 ... */
uint32_t sampt1; /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31>ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ÿ<EFBFBD><C3BF>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD>һ
@arg ADC_SAMPTIME_3CYCLES ... */
uint32_t sampt2; /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32>ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ÿ<EFBFBD><C3BF>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD>һ
@arg ADC_SAMPTIME_3CYCLES ... */
uint32_t overrun_mode; /**< ת<><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC_DR<44>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ洢<DDB4><E6B4A2>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
@arg ADC_OVRN_MODE_PRESERVED ... */
uint32_t conver_mode; /**< ת<><D7AA>ģʽѡ<CABD>񣬿<EFBFBD><F1A3ACBF><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ɨ<EFBFBD>衢ѭ<E8A1A2><D1AD>ɨ<EFBFBD>衢ѭ<E8A1A2><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>ģʽ
@arg ADC_SINGLE_CONVER_MODE ... */
uint32_t scan_dir; /**< ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɨ<EFBFBD>跽<EFBFBD><E8B7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
@arg ADC_SCAN_DIR_FORWARD ... */
} std_adc_init_t;
/**
* @}
*/
/*--------------------------------------------define--------------------------------------------*/
/************************************************************************************************/
/**
* @defgroup ADC_Constants ADC Constants
* @brief ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>弰<EFBFBD>궨<EFBFBD><EFBFBD>
* @{
*
*/
/************************************************************************************************/
/* ADCʱ<43><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>Ƶϵ<C6B5><CFB5> */
#define ADC_SYNC_CLK_PCLK_DIV1 ADC_CFG2_CKSRC_PCLK /**< ADCͬ<43><CDAC>ʱ<EFBFBD><CAB1>: PCLK<4C><4B><EFBFBD><EFBFBD>Ƶ */
#define ADC_SYNC_CLK_PCLK_DIV2 ADC_CFG2_CKSRC_PCLK_DIV2 /**< ADCͬ<43><CDAC>ʱ<EFBFBD><CAB1>: PCLK/2<><32>Ƶ */
#define ADC_SYNC_CLK_PCLK_DIV4 ADC_CFG2_CKSRC_PCLK_DIV4 /**< ADCͬ<43><CDAC>ʱ<EFBFBD><CAB1>: PCLK/4<><34>Ƶ */
#define ADC_ASYNC_CLK_KCLK ADC_CFG2_CKSRC_KCLK /**< ADC<44>첽ʱ<ECB2BD><CAB1>: KCLK */
/* ADC<44>첽ʱ<ECB2BD>ӷ<EFBFBD>Ƶϵ<C6B5><CFB5> */
#define ADC_ASYNC_CLK_DIV1 ADC_CFG2_PRESC_DIV1 /**< ADC<44>첽ʱ<ECB2BD><CAB1>: <20><><EFBFBD><EFBFBD>Ƶ */
#define ADC_ASYNC_CLK_DIV2 ADC_CFG2_PRESC_DIV2 /**< ADC<44>첽ʱ<ECB2BD><CAB1>: 2<><32>Ƶ */
#define ADC_ASYNC_CLK_DIV4 ADC_CFG2_PRESC_DIV4 /**< ADC<44>첽ʱ<ECB2BD><CAB1>: 4<><34>Ƶ */
#define ADC_ASYNC_CLK_DIV6 ADC_CFG2_PRESC_DIV6 /**< ADC<44>첽ʱ<ECB2BD><CAB1>: 6<><36>Ƶ */
#define ADC_ASYNC_CLK_DIV8 ADC_CFG2_PRESC_DIV8 /**< ADC<44>첽ʱ<ECB2BD><CAB1>: 8<><38>Ƶ */
#define ADC_ASYNC_CLK_DIV10 ADC_CFG2_PRESC_DIV10 /**< ADC<44>첽ʱ<ECB2BD><CAB1>: 10<31><30>Ƶ */
#define ADC_ASYNC_CLK_DIV12 ADC_CFG2_PRESC_DIV12 /**< ADC<44>첽ʱ<ECB2BD><CAB1>: 12<31><32>Ƶ */
#define ADC_ASYNC_CLK_DIV16 ADC_CFG2_PRESC_DIV16 /**< ADC<44>첽ʱ<ECB2BD><CAB1>: 16<31><36>Ƶ */
#define ADC_ASYNC_CLK_DIV32 ADC_CFG2_PRESC_DIV32 /**< ADC<44>첽ʱ<ECB2BD><CAB1>: 32<33><32>Ƶ */
#define ADC_ASYNC_CLK_DIV64 ADC_CFG2_PRESC_DIV64 /**< ADC<44>첽ʱ<ECB2BD><CAB1>: 64<36><34>Ƶ */
#define ADC_ASYNC_CLK_DIV128 ADC_CFG2_PRESC_DIV128 /**< ADC<44>첽ʱ<ECB2BD><CAB1>: 128<32><38>Ƶ */
/* ADCת<43><D7AA>ģʽ */
#define ADC_SINGLE_CONVER_MODE ADC_CFG1_CONV_MOD_SINGLE /**< ADC<44><43><EFBFBD><EFBFBD>ɨ<EFBFBD><C9A8>ת<EFBFBD><D7AA> */
#define ADC_CONTINUOUS_CONVER_MODE ADC_CFG1_CONV_MOD_CONTINUOUS /**< ADCѭ<43><D1AD>ɨ<EFBFBD><C9A8>ת<EFBFBD><D7AA> */
#define ADC_DISCONTINUOUS_CONVER_MODE ADC_CFG1_CONV_MOD_DISCONTINUOUS /**< ADCѭ<43><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA> */
/* ADCͨ<43><CDA8>ɨ<EFBFBD>跽<EFBFBD><E8B7BD> */
#define ADC_SCAN_DIR_FORWARD (0x00000000U) /**< ADCת<43><D7AA>ͨ<EFBFBD><CDA8>: <20><><EFBFBD><EFBFBD>ɨ<EFBFBD><C9A8> */
#define ADC_SCAN_DIR_BACKWARD ADC_CFG1_SDIR /**< ADCת<43><D7AA>ͨ<EFBFBD><CDA8>: <20><><EFBFBD><EFBFBD>ɨ<EFBFBD><C9A8> */
/* ADCת<43><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_TRIG_SW ADC_CFG1_TRIGEN_SW /**< <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ */
#define ADC_TRIG_HW_EDGE_RISING ADC_CFG1_TRIGEN_HW_EDGE_RISING /**< <20>ⲿӲ<E2B2BF><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>: <20><><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD> */
#define ADC_TRIG_HW_EDGE_FALLING ADC_CFG1_TRIGEN_HW_EDGE_FALLING /**< <20>ⲿӲ<E2B2BF><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>: <20>½<EFBFBD><C2BD>ش<EFBFBD><D8B4><EFBFBD> */
#define ADC_TRIG_HW_EDGE_BOTH ADC_CFG1_TRIGEN_HW_EDGE_BOTH /**< <20>ⲿӲ<E2B2BF><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>: ˫<>ش<EFBFBD><D8B4><EFBFBD> */
/* ADCת<43><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ */
#define ADC_EXTRIG_TIM3_TRGO ADC_CFG1_TRIG_TIM3_TRGO /**< ADC<44><43><EFBFBD><EFBFBD>Դ: TIM3 TRGO */
#define ADC_EXTRIG_TIM4_TRGO ADC_CFG1_TRIG_TIM4_TRGO /**< ADC<44><43><EFBFBD><EFBFBD>Դ: TIM4 TRGO */
#define ADC_EXTRIG_TIM5_TRGO ADC_CFG1_TRIG_TIM5_TRGO /**< ADC<44><43><EFBFBD><EFBFBD>Դ: TIM5 TRGO */
#define ADC_EXTRIG_TIM8_TRGO ADC_CFG1_TRIG_TIM8_TRGO /**< ADC<44><43><EFBFBD><EFBFBD>Դ: TIM8 TRGO */
#define ADC_EXTRIG_EXTI2 ADC_CFG1_TRIG_EXTI2 /**< ADC<44><43><EFBFBD><EFBFBD>Դ: <20>ⲿ<EFBFBD>ж<EFBFBD>EXTI_2 */
#define ADC_EXTRIG_EXTI11 ADC_CFG1_TRIG_EXTI11 /**< ADC<44><43><EFBFBD><EFBFBD>Դ: <20>ⲿ<EFBFBD>ж<EFBFBD>EXTI_11 */
/* ADCת<43><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC_DR<44>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ洢<DDB4><E6B4A2>ʽ */
#define ADC_OVRN_MODE_PRESERVED (0x00000000U) /**< ADC_DR<44>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD><EFBFBD><EFBFBD> */
#define ADC_OVRN_MODE_OVERWRITTEN ADC_CFG1_OVRN_MOD /**< ADC_DR<44>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/* ADCת<43><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_GROUP_1 (0U) /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1 */
#define ADC_SAMPTIME_GROUP_2 (4U) /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2 */
/* ADC<44><43><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_3CYCLES ADC_SAMPT_SAMPT1_3CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ3<CEAA><33>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_7CYCLES ADC_SAMPT_SAMPT1_7CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ7<CEAA><37>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_12CYCLES ADC_SAMPT_SAMPT1_12CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ12<31><32>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_19CYCLES ADC_SAMPT_SAMPT1_19CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ19<31><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_39CYCLES ADC_SAMPT_SAMPT1_39CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ39<33><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_79CYCLES ADC_SAMPT_SAMPT1_79CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ79<37><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_119CYCLES ADC_SAMPT_SAMPT1_119CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ119<31><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_159CYCLES ADC_SAMPT_SAMPT1_159CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ159<35><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_239CYCLES ADC_SAMPT_SAMPT1_239CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ239<33><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_319CYCLES ADC_SAMPT_SAMPT1_319CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ319<31><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_479CYCLES ADC_SAMPT_SAMPT1_479CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ479<37><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_639CYCLES ADC_SAMPT_SAMPT1_639CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ639<33><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_959CYCLES ADC_SAMPT_SAMPT1_959CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ959<35><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_1279CYCLES ADC_SAMPT_SAMPT1_1279CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ1279<37><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_SAMPTIME_1919CYCLES ADC_SAMPT_SAMPT1_1919CYCLES /**< <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ1919<31><39>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/* ADCת<43><D7AA>ͨ<EFBFBD><CDA8> */
#define ADC_CHANNEL_NONE (0x00000000U) /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_CHANNEL_0 ADC_CHCFG_CHN0 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN0 */
#define ADC_CHANNEL_1 ADC_CHCFG_CHN1 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN1 */
#define ADC_CHANNEL_2 ADC_CHCFG_CHN2 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN2 */
#define ADC_CHANNEL_3 ADC_CHCFG_CHN3 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN3 */
#define ADC_CHANNEL_4 ADC_CHCFG_CHN4 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN4 */
#define ADC_CHANNEL_5 ADC_CHCFG_CHN5 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN5 */
#define ADC_CHANNEL_6 ADC_CHCFG_CHN6 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN6 */
#define ADC_CHANNEL_7 ADC_CHCFG_CHN7 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN7 */
#define ADC_CHANNEL_8 ADC_CHCFG_CHN8 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN8 */
#define ADC_CHANNEL_9 ADC_CHCFG_CHN9 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN9 */
#define ADC_CHANNEL_10 ADC_CHCFG_CHN10 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN10 */
#define ADC_CHANNEL_11 ADC_CHCFG_CHN11 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN11 */
#define ADC_CHANNEL_12 ADC_CHCFG_CHN12 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN12 */
#define ADC_CHANNEL_13 ADC_CHCFG_CHN13 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN13 */
#define ADC_CHANNEL_14 ADC_CHCFG_CHN14 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN14 */
#define ADC_CHANNEL_15 ADC_CHCFG_CHN15 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN15 */
#define ADC_CHANNEL_16 ADC_CHCFG_CHN16 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN16 */
#define ADC_CHANNEL_19 ADC_CHCFG_CHN19 /**< ADC ת<><D7AA>ͨ<EFBFBD><CDA8>IN19 */
#define ADC_CHANNEL_VTS ADC_CHCFG_CHN12 /**< ADC <20>ڲ<EFBFBD>ת<EFBFBD><D7AA>ͨ<EFBFBD><CDA8>VTS */
#define ADC_CHANNEL_VBGR ADC_CHCFG_CHN13 /**< ADC <20>ڲ<EFBFBD>ת<EFBFBD><D7AA>ͨ<EFBFBD><CDA8>VBGR */
#define ADC_CHANNEL_VBAT_DIV3 ADC_CHCFG_CHN14 /**< ADC <20>ڲ<EFBFBD>ת<EFBFBD><D7AA>ͨ<EFBFBD><CDA8>VBAT/3 */
#define ADC_CHANNEL_VDDA_DIV3 ADC_CHCFG_CHN14 /**< ADC <20>ڲ<EFBFBD>ת<EFBFBD><D7AA>ͨ<EFBFBD><CDA8>VDDA/3 */
#define ADC_CHANNEL_ALL ADC_CHCFG_CHN /**< ADC ȫ<><C8AB>ת<EFBFBD><D7AA>ͨ<EFBFBD><CDA8> */
/* ADCģ<43>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8> */
#define ADC_AWDG_CHANNEL_NONE (0x00000000U) /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_AWDG_CHANNEL_0 ADC_AWDG1CR_AWDG1_CHN0 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>0 */
#define ADC_AWDG_CHANNEL_1 ADC_AWDG1CR_AWDG1_CHN1 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>1 */
#define ADC_AWDG_CHANNEL_2 ADC_AWDG1CR_AWDG1_CHN2 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>2 */
#define ADC_AWDG_CHANNEL_3 ADC_AWDG1CR_AWDG1_CHN3 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>3 */
#define ADC_AWDG_CHANNEL_4 ADC_AWDG1CR_AWDG1_CHN4 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>4 */
#define ADC_AWDG_CHANNEL_5 ADC_AWDG1CR_AWDG1_CHN5 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>5 */
#define ADC_AWDG_CHANNEL_6 ADC_AWDG1CR_AWDG1_CHN6 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>6 */
#define ADC_AWDG_CHANNEL_7 ADC_AWDG1CR_AWDG1_CHN7 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>7 */
#define ADC_AWDG_CHANNEL_8 ADC_AWDG1CR_AWDG1_CHN8 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>8 */
#define ADC_AWDG_CHANNEL_9 ADC_AWDG1CR_AWDG1_CHN9 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>9 */
#define ADC_AWDG_CHANNEL_10 ADC_AWDG1CR_AWDG1_CHN10 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>10 */
#define ADC_AWDG_CHANNEL_11 ADC_AWDG1CR_AWDG1_CHN11 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>11 */
#define ADC_AWDG_CHANNEL_12 ADC_AWDG1CR_AWDG1_CHN12 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>12 */
#define ADC_AWDG_CHANNEL_13 ADC_AWDG1CR_AWDG1_CHN13 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>13 */
#define ADC_AWDG_CHANNEL_14 ADC_AWDG1CR_AWDG1_CHN14 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>14 */
#define ADC_AWDG_CHANNEL_15 ADC_AWDG1CR_AWDG1_CHN15 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>15 */
#define ADC_AWDG_CHANNEL_16 ADC_AWDG1CR_AWDG1_CHN16 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>16 */
#define ADC_AWDG_CHANNEL_19 ADC_AWDG1CR_AWDG1_CHN19 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>19 */
#define ADC_AWDG_CHANNEL_VTS ADC_AWDG1CR_AWDG1_CHN12 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>VTS */
#define ADC_AWDG_CHANNEL_VBGR ADC_AWDG1CR_AWDG1_CHN13 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>VBGR */
#define ADC_AWDG_CHANNEL_VBAT_DIV3 ADC_AWDG1CR_AWDG1_CHN14 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>VBAT/3 */
#define ADC_AWDG_CHANNEL_VDDA_DIV3 ADC_AWDG1CR_AWDG1_CHN14 /**< ADC ģ<>⿴<EFBFBD>Ź<EFBFBD><C5B9><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>VDDA/3 */
#define ADC_AWDG_CHANNEL_ALL ADC_AWDG1CR_AWDG1_CHN /**< ADC ȫ<><C8AB>ת<EFBFBD><D7AA>ͨ<EFBFBD><CDA8> */
/* ADC<44>ڲ<EFBFBD>ͨ<EFBFBD><CDA8>ʹ<EFBFBD><CAB9> */
#define ADC_INTERNAL_CHANNEL_NONE (0x00000000U) /**< ADC <20>ڲ<EFBFBD>ͨ<EFBFBD><CDA8>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD>ֹ */
#define ADC_INTERNAL_CHANNEL_VBGREN ADC_CFG2_VBGREN /**< ADC <20>ڲ<EFBFBD>ͨ<EFBFBD><CDA8>VBGRʹ<52><CAB9> */
#define ADC_INTERNAL_CHANNEL_VTSEN ADC_CFG2_VTSEN /**< ADC <20>ڲ<EFBFBD>ͨ<EFBFBD><CDA8>VTSʹ<53><CAB9> */
#define ADC_INTERNAL_CHANNEL_VBAT_DIV3 ADC_CFG2_VBAT_DIV3 /**< ADC <20>ڲ<EFBFBD>ͨ<EFBFBD><CDA8>VBAT/3ʹ<33><CAB9> */
#define ADC_INTERNAL_CHANNEL_VDDA_DIV3 ADC_CFG2_VDDA_DIV3 /**< ADC <20>ڲ<EFBFBD>ͨ<EFBFBD><CDA8>VDDA/3ʹ<33><CAB9> */
/* ADC<44>ж<EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>壺IER<45>жϼĴ<CFBC><C4B4><EFBFBD> */
#define ADC_INTERRUPT_EOSAMP ADC_IER_EOSAMPIE /**< ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD> */
#define ADC_INTERRUPT_EOC ADC_IER_EOCIE /**< ADC<44><43>ͨ<EFBFBD><CDA8>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD> */
#define ADC_INTERRUPT_EOS ADC_IER_EOSIE /**< ADCͨ<43><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD> */
#define ADC_INTERRUPT_OVRN ADC_IER_OVRNIE /**< ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD> */
#define ADC_INTERRUPT_AWDG1 ADC_IER_AWDG1IE /**< ADCģ<43>⿴<EFBFBD>Ź<EFBFBD>1<EFBFBD><31>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD> */
#define ADC_INTERRUPT_EOCAL ADC_IER_EOCALIE /**< ADCУ׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD> */
/* ADC״̬<D7B4><CCAC><EFBFBD>壺ISR״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD> */
#define ADC_FLAG_EOSAMP ADC_ISR_EOSAMP /**< ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬ */
#define ADC_FLAG_EOC ADC_ISR_EOC /**< ADC<44><43>ͨ<EFBFBD><CDA8>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬ */
#define ADC_FLAG_EOS ADC_ISR_EOS /**< ADCͨ<43><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬ */
#define ADC_FLAG_OVRN ADC_ISR_OVRN /**< ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬ */
#define ADC_FLAG_AWDG1 ADC_ISR_AWDG1 /**< ADCģ<43>⿴<EFBFBD>Ź<EFBFBD>1<EFBFBD><31><EFBFBD>ص<EFBFBD>ѹ״̬ */
#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /**< ADCУ׼״̬ */
#define ADC_FLAG_ALL (ADC_ISR_EOSAMP | ADC_ISR_EOC | ADC_ISR_EOS \
| ADC_ISR_OVRN | ADC_ISR_AWDG1 | ADC_ISR_EOCAL) /**< ADCȫ<43><C8AB>״̬ */
/* VBGRУ׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define VBGR_CAL_ADDR ((uint16_t*)(BGR_CAL)) /**< VBGRУ׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2>ַ */
#define VBGR_CAL_VREF (3300U) /**< VBGRУ׼<D0A3><D7BC><EFBFBD>òο<C3B2><CEBF><EFBFBD>ѹ<EFBFBD><D1B9>3.3V */
/* <20>¶ȴ<C2B6><C8B4><EFBFBD><EFBFBD><EFBFBD>У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define TS_CAL_ADDR_25 ((uint16_t*)(TS_CAL_25)) /**< <20>¶ȴ<C2B6><C8B4><EFBFBD><EFBFBD><EFBFBD>У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2>ַ<EFBFBD><D6B7>25<32><35> */
#define TS_CAL_ADDR_85 ((uint16_t*)(TS_CAL_85)) /**< <20>¶ȴ<C2B6><C8B4><EFBFBD><EFBFBD><EFBFBD>У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2>ַ<EFBFBD><D6B7>85<38><35> */
#define TS_CAL_TEMP_25 ((int32_t)25U) /**< <20>¶ȴ<C2B6><C8B4><EFBFBD><EFBFBD><EFBFBD>У׼<D0A3>ȣ<C2B6>25<32><35> */
#define TS_CAL_TEMP_85 ((int32_t)85U) /**< <20>¶ȴ<C2B6><C8B4><EFBFBD><EFBFBD><EFBFBD>У׼<D0A3>ȣ<C2B6>85<38><35> */
#define TS_CAL_VREF (3300U) /**< <20>¶ȴ<C2B6><C8B4><EFBFBD><EFBFBD><EFBFBD>У׼<D0A3><D7BC><EFBFBD>òο<C3B2><CEBF><EFBFBD>ѹ<EFBFBD><D1B9>3.3V */
/* <20>ȴ<EFBFBD><C8B4>ڲ<EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><CAB1>
VBGRͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><EFBFBD> 15US
VTSͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><EFBFBD> 18US
VBAT_DIV3<EFBFBD><EFBFBD>VDDA_DIV3ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><EFBFBD> 15US
<EFBFBD><EFBFBD><EFBFBD>ö<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD>ͨ<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD>伴<EFBFBD><EFBFBD>
*/
#define ADC_VBGR_CHANNEL_DELAY (15U) /**< VBGRͨ<52><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><CAB1> */
#define ADC_VTS_CHANNEL_DELAY (18U) /**< VTSͨ<53><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><CAB1> */
#define ADC_VBAT_DIV3_CHANNEL_DELAY (15U) /**< VBAT/3ͨ<33><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><CAB1> */
#define ADC_VDDA_DIV3_CHANNEL_DELAY (15U) /**< VDDA/3ͨ<33><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><CAB1> */
/* ADCʹ<43><CAB9><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><CAB1>
<EFBFBD><EFBFBD>ADC_CKʱ<EFBFBD>Ӵ<EFBFBD><EFBFBD>ڵ<EFBFBD><EFBFBD><EFBFBD>6MHz<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD>2.5us<EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><EFBFBD>
<EFBFBD><EFBFBD>ADC_CKʱ<EFBFBD><EFBFBD>С<EFBFBD><EFBFBD>6MHz<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD>17<EFBFBD><EFBFBD>ADCʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><EFBFBD>
*/
#define ADC_EN_DELAY (3U) /**< ADCʹ<43><CAB9><EFBFBD>ȶ<EFBFBD>ʱ<EFBFBD><CAB1> */
/* ADC<44>ο<EFBFBD><CEBF><EFBFBD>ѹԴ */
#define ADC_REFERENCE_VREFBUF (0x00000000U) /**< VRFEBUF<55><46><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>ο<EFBFBD><CEBF><EFBFBD>ѹԴ<D1B9><D4B4><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>VREFBUF<55><46><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PA0<41><30><EFBFBD><EFBFBD>Ϊģ<CEAA><C4A3>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1uF+0.1uF<EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define ADC_REFERENCE_VREFP (0x00000000U) /**< VREF+<2B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>ο<EFBFBD><CEBF><EFBFBD>ѹԴ<D1B9><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PA0<41><30><EFBFBD><EFBFBD>Ϊģ<CEAA><C4A3>ģʽ */
#define ADC_REFERENCE_VDDA ADC_CFG2_REF /**< VDDA<44><41>Ϊ<EFBFBD>ο<EFBFBD><CEBF><EFBFBD>ѹԴ */
/* ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ */
#define ADC_CONVER_SCALE (4095U) /**< ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<44><43>ѹת<D1B9><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<EFBFBD>ɼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param VREF <EFBFBD>ο<EFBFBD><EFBFBD><EFBFBD>ѹ
* @param TS_DATA ADC<EFBFBD>ɼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹֵ
* @retval <EFBFBD>ȴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
#define ADC_CALC_TEMPERATURE(VREF, TS_DATA) \
((((((int32_t)((TS_DATA * VREF) / TS_CAL_VREF) \
- (int32_t) *TS_CAL_ADDR_25)) \
* (int32_t)(TS_CAL_TEMP_85 - TS_CAL_TEMP_25)) \
/ (int32_t)((int32_t)*TS_CAL_ADDR_85 - (int32_t)*TS_CAL_ADDR_25)) \
+ TS_CAL_TEMP_25)
/**
* @}
*/
/*-------------------------------------------functions------------------------------------------*/
/************************************************************************************************/
/**
* @defgroup ADC_External_Functions ADC External Functions
* @brief ADC<EFBFBD><EFBFBD><EFBFBD>⺯<EFBFBD><EFBFBD>
* @{
*
*/
/************************************************************************************************/
/**
* @brief ʹ<EFBFBD><EFBFBD>ADC
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_enable(void)
{
ADC->CR = (ADC_CR_ADEN);
}
/**
* @brief <EFBFBD><EFBFBD>ֹADC
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_disable(void)
{
ADC->CR = (ADC_CR_ADDIS);
}
/**
* @brief <EFBFBD><EFBFBD>ȡADCʹ<EFBFBD><EFBFBD>λ״̬
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>жϽ<EFBFBD><EFBFBD><EFBFBD>
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>״̬
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾADC<EFBFBD><EFBFBD><EFBFBD>ڽ<EFBFBD>ֹ״̬
*/
__STATIC_INLINE bool std_adc_get_enable_status(void)
{
return ((ADC->CR & ADC_CR_ADEN) == ADC_CR_ADEN);
}
/**
* @brief ʹ<EFBFBD><EFBFBD>ADC<EFBFBD><EFBFBD>DMA<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_dma_enable(void)
{
ADC->CFG1 |= (ADC_CFG1_DMAEN);
}
/**
* @brief <EFBFBD><EFBFBD>ֹADC<EFBFBD><EFBFBD>DMA<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_dma_disable(void)
{
ADC->CFG1 &= (~ADC_CFG1_DMAEN);
}
/**
* @brief <EFBFBD><EFBFBD>ȡADC<EFBFBD><EFBFBD>DMAλʹ<EFBFBD><EFBFBD>״̬
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>жϽ<EFBFBD><EFBFBD><EFBFBD>
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾADC<EFBFBD><EFBFBD>DMA<EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾADC<EFBFBD><EFBFBD>DMAδʹ<EFBFBD><EFBFBD>
*/
__STATIC_INLINE bool std_adc_get_dma_status(void)
{
return((ADC->CFG1 & ADC_CFG1_DMAEN) == ADC_CFG1_DMAEN);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCʱ<EFBFBD><EFBFBD>Դ
* @param clock_src ADCʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg ADC_SYNC_CLK_PCLK_DIV1<EFBFBD><EFBFBD>PCLK<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ
* @arg ADC_SYNC_CLK_PCLK_DIV2<EFBFBD><EFBFBD>PCLK 2<EFBFBD><EFBFBD>Ƶ
* @arg ADC_SYNC_CLK_PCLK_DIV4<EFBFBD><EFBFBD>PCLK 4<EFBFBD><EFBFBD>Ƶ
* @arg ADC_ASYNC_CLK_KCLK<EFBFBD><EFBFBD>KCLK
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_clock_source_config(uint32_t clock_src)
{
MODIFY_REG(ADC->CFG2, ADC_CFG2_CKSRC, clock_src);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<EFBFBD>첽ʱ<EFBFBD>ӷ<EFBFBD>Ƶ
* @param presc ADC<EFBFBD>첽ʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD>
* @arg ADC_ASYNC_CLK_DIV1<EFBFBD><EFBFBD>ADC_KCLK<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ
* @arg ADC_ASYNC_CLK_DIV2<EFBFBD><EFBFBD>ADC_KCLK 2<EFBFBD><EFBFBD>Ƶ
* @arg ADC_ASYNC_CLK_DIV4<EFBFBD><EFBFBD>ADC_KCLK 4<EFBFBD><EFBFBD>Ƶ
* @arg ...
* @arg ADC_ASYNC_CLK_DIV128<EFBFBD><EFBFBD>ADC_KCLK 128<EFBFBD><EFBFBD>Ƶ
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_asynchronous_clock_config(uint32_t presc)
{
MODIFY_REG(ADC->CFG2, ADC_CFG2_PRESC, presc);
}
/**
* @brief ʹ<EFBFBD><EFBFBD>ADCУ׼
* @note <EFBFBD><EFBFBD>ADEN=1<EFBFBD><EFBFBD>ADC<EFBFBD>ȶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>START=0<EFBFBD><EFBFBD>STOP=0<EFBFBD><EFBFBD>ADDIS=0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CALENλ<EFBFBD><EFBFBD>1
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_calibration_enable(void)
{
ADC->CR = (ADC_CR_CALEN);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCת<EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_start_conversion(void)
{
ADC->CR = (ADC_CR_START);
}
/**
* @brief <EFBFBD><EFBFBD>ȡADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>жϽ<EFBFBD><EFBFBD><EFBFBD>
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڹ<EFBFBD><EFBFBD><EFBFBD>״̬
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD>δ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
*/
__STATIC_INLINE bool std_adc_get_conversion_status(void)
{
return ((ADC->CR & ADC_CR_START) == ADC_CR_START);
}
/**
* @brief ADCֹͣת<EFBFBD><EFBFBD>
* @note <EFBFBD><EFBFBD><EFBFBD><EFBFBD>START=1<EFBFBD><EFBFBD>ADDIS=0ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>STOPλ<EFBFBD><EFBFBD>1<EFBFBD><EFBFBD>Ч
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_stop_conversion(void)
{
ADC->CR = (ADC_CR_STOP);
}
/**
* @brief ADC<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><EFBFBD>
* @param interrupt ADC<EFBFBD>ж<EFBFBD>Դ
* @arg ADC_INTERRUPT_EOSAMP
* @arg ADC_INTERRUPT_EOC
* @arg ADC_INTERRUPT_EOS
* @arg ADC_INTERRUPT_OVRN
* @arg ADC_INTERRUPT_AWDG1
* @arg ADC_INTERRUPT_EOCAL
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_interrupt_enable(uint32_t interrupt)
{
ADC->IER |= (interrupt);
}
/**
* @brief ADC<EFBFBD>жϽ<EFBFBD>ֹ
* @param interrupt ADC<EFBFBD>ж<EFBFBD>Դ
* @arg ADC_INTERRUPT_EOSAMP
* @arg ADC_INTERRUPT_EOC
* @arg ADC_INTERRUPT_EOS
* @arg ADC_INTERRUPT_OVRN
* @arg ADC_INTERRUPT_AWDG1
* @arg ADC_INTERRUPT_EOCAL
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_interrupt_disable(uint32_t interrupt)
{
ADC->IER &= (~interrupt);
}
/**
* @brief <EFBFBD><EFBFBD>ȡADC<EFBFBD>ж<EFBFBD>Դʹ<EFBFBD><EFBFBD>״̬
* @param interrupt ADC<EFBFBD>ж<EFBFBD>Դ<EFBFBD><EFBFBD>Ϣ
* @arg ADC_INTERRUPT_EOSAMP
* @arg ADC_INTERRUPT_EOC
* @arg ADC_INTERRUPT_EOS
* @arg ADC_INTERRUPT_OVRN
* @arg ADC_INTERRUPT_AWDG1
* @arg ADC_INTERRUPT_EOCAL
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>жϽ<EFBFBD><EFBFBD><EFBFBD>
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʹ<EFBFBD><EFBFBD>
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>δʹ<EFBFBD><EFBFBD>
*/
__STATIC_INLINE bool std_adc_get_interrupt_enable(uint32_t interrupt)
{
return((ADC->IER & (interrupt)) == (interrupt));
}
/**
* @brief <EFBFBD><EFBFBD>ȡADC<EFBFBD><EFBFBD>־״̬
* @param flag <EFBFBD><EFBFBD>ȡADC<EFBFBD><EFBFBD>־
* @arg ADC_FLAG_EOSAMP
* @arg ADC_FLAG_EOC
* @arg ADC_FLAG_EOS
* @arg ADC_FLAG_OVRN
* @arg ADC_FLAG_AWDG1
* @arg ADC_FLAG_EOCAL
* @retval bool <EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD>־λ״̬
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾ<EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD>־Ϊ<EFBFBD><EFBFBD>λ״̬
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD>־Ϊ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
*/
__STATIC_INLINE bool std_adc_get_flag(uint32_t flag)
{
return((ADC->ISR & (flag)) == (flag));
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<EFBFBD><EFBFBD>־
* @param flag <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<EFBFBD><EFBFBD>־
* @arg ADC_FLAG_EOSAMP
* @arg ADC_FLAG_EOC
* @arg ADC_FLAG_EOS
* @arg ADC_FLAG_OVRN
* @arg ADC_FLAG_AWDG1
* @arg ADC_FLAG_EOCAL
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_clear_flag(uint32_t flag)
{
ADC->ISR = (flag);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCת<EFBFBD><EFBFBD>ģʽ
* @param conversion_mode ת<EFBFBD><EFBFBD>ģʽѡ<EFBFBD><EFBFBD>
* @arg ADC_SINGLE_CONVER_MODE
* @arg ADC_CONTINUOUS_CONVER_MODE
* @arg ADC_DISCONTINUOUS_CONVER_MODE
* @note <EFBFBD><EFBFBD>START=0ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD>λ<EFBFBD><EFBFBD>ִ<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_conversion_mode_config(uint32_t conversion_mode)
{
MODIFY_REG(ADC->CFG1, ADC_CFG1_CONV_MOD, conversion_mode);
}
/**
* @brief ADCͨ<EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>
* @param channel ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
* @arg ADC_CHANNEL_NONE
* @arg ADC_CHANNEL_0
* @arg ...
* @arg ADC_CHANNEL_ALL
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_fix_sequence_channel_enable(uint32_t channel)
{
ADC->CHCFG |= (channel);
}
/**
* @brief ADCͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ
* @param channel <EFBFBD><EFBFBD>ֹͨ<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
* @arg ADC_CHANNEL_0
* @arg ADC_CHANNEL_1
* @arg ...
* @arg ADC_CHANNEL_ALL
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_fix_sequence_channel_disable(uint32_t channel)
{
ADC->CHCFG &= (~channel);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD>ͼ<EFBFBD><EFBFBD><EFBFBD>
* @param trig_edge <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
* @arg ADC_TRIG_SW(<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ)
* @arg ADC_TRIG_HW_EDGE_RISING
* @arg ADC_TRIG_HW_EDGE_FALLING
* @arg ADC_TRIG_HW_EDGE_BOTH
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_trig_edge_config(uint32_t trig_edge)
{
MODIFY_REG(ADC->CFG1, ADC_CFG1_TRIGEN, trig_edge);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<EFBFBD>ⲿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ
* @param trig_source <EFBFBD>ⲿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
* @arg ADC_EXTRIG_TIM3_TRGO
* @arg ADC_EXTRIG_TIM4_TRGO
* @arg ADC_EXTRIG_TIM5_TRGO
* @arg ADC_EXTRIG_TIM8_TRGO
* @arg ADC_EXTRIG_EXTI2
* @arg ADC_EXTRIG_EXTI11
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_external_trig_source_config(uint32_t trig_source)
{
MODIFY_REG(ADC->CFG1, ADC_CFG1_TRIG_SEL, trig_source);
}
/**
* @brief ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param sample_time <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
* @arg ADC_SAMPTIME_3CYCLES
* @arg ...
* @arg ADC_SAMPTIME_1919CYCLES
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_sampt1_time_config(uint32_t sample_time)
{
MODIFY_REG(ADC->SAMPT, ADC_SAMPT_SAMPT1, sample_time);
}
/**
* @brief ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param sample_time <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
* @arg ADC_SAMPTIME_3CYCLES
* @arg ...
* @arg ADC_SAMPTIME_1919CYCLES
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_sampt2_time_config(uint32_t sample_time)
{
MODIFY_REG(ADC->SAMPT, ADC_SAMPT_SAMPT2, sample_time << ADC_SAMPT_SAMPT2_POS);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
* @param samptx <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
* @arg ADC_SAMPTIME_GROUP_1
* @arg ADC_SAMPTIME_GROUP_2
* @param channel ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
* @arg ADC_CHANNEL_0
* @arg ADC_CHANNEL_1
* @arg ...
* @arg ADC_CHANNEL_VBAT_DIV3
* @arg ADC_CHANNEL_VDDA_DIV3
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_channel_sample_time_select(uint32_t samptx, uint32_t channel)
{
if(samptx == ADC_SAMPTIME_GROUP_1)
{
ADC->SAMPT &= (~(channel << ADC_SAMPT_SAMPT_SEL_POS));
}
else
{
ADC->SAMPT |= (channel << ADC_SAMPT_SAMPT_SEL_POS);
}
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCУ׼ϵ<EFBFBD><EFBFBD>
* @param calibration_factor <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΧΪ0x00~0x3F
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_calibration_factor_config(uint32_t calibration_factor)
{
ADC->CALFACT = calibration_factor;
}
/**
* @brief ʹ<EFBFBD><EFBFBD>ADC<EFBFBD>ȴ<EFBFBD>ģʽ
* @note <EFBFBD><EFBFBD><EFBFBD>ڱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>δ<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>ȡ<EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_wait_mode_enable(void)
{
ADC->CFG1 |= (ADC_CFG1_WAIT_MOD);
}
/**
* @brief <EFBFBD><EFBFBD>ֹADC<EFBFBD>ȴ<EFBFBD>ģʽ
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_wait_mode_disable(void)
{
ADC->CFG1 &= (~ADC_CFG1_WAIT_MOD);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɨ<EFBFBD>跽<EFBFBD><EFBFBD>
* @param dir ADCͨ<EFBFBD><EFBFBD>ɨ<EFBFBD>跽<EFBFBD><EFBFBD>
* @arg ADC_SCAN_DIR_FORWARD
* @arg ADC_SCAN_DIR_BACKWARD
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_scan_direction_config(uint32_t dir)
{
MODIFY_REG(ADC->CFG1, ADC_CFG1_SDIR, dir);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ
* @param ovrn_mode ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ
* @arg ADC_OVRN_MODE_PRESERVED
* @arg ADC_OVRN_MODE_OVERWRITTEN
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_ovrn_mode_config(uint32_t ovrn_mode)
{
MODIFY_REG(ADC->CFG1, ADC_CFG1_OVRN_MOD, ovrn_mode);
}
/**
* @brief ADC<EFBFBD>ڲ<EFBFBD>ͨ<EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>
* @param inter_channel ADC<EFBFBD>ڲ<EFBFBD>ͨ<EFBFBD><EFBFBD>
* @arg ADC_INTERNAL_CHANNEL_VBGREN
* @arg ADC_INTERNAL_CHANNEL_VTSEN
* @arg ADC_INTERNAL_CHANNEL_VBAT_DIV3
* @arg ADC_INTERNAL_CHANNEL_VDDA_DIV3
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_internal_channel_enable(uint32_t inter_channel)
{
ADC->CFG2 |= (inter_channel);
}
/**
* @brief ADC<EFBFBD>ڲ<EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ
* @param inter_channel ADC<EFBFBD>ڲ<EFBFBD>ͨ<EFBFBD><EFBFBD>
* @arg ADC_INTERNAL_CHANNEL_VBGREN
* @arg ADC_INTERNAL_CHANNEL_VTSEN
* @arg ADC_INTERNAL_CHANNEL_VBAT_DIV3
* @arg ADC_INTERNAL_CHANNEL_VDDA_DIV3
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_internal_channel_disable(uint32_t inter_channel)
{
ADC->CFG2 &= (~inter_channel);
}
/**
* @brief ѡ<EFBFBD><EFBFBD>ADCģ<EFBFBD>⿴<EFBFBD>Ź<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD>
* @param channel ADC<EFBFBD><EFBFBD><EFBFBD>Ź<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
* @arg ADC_AWDG_CHANNEL_NONE
* @arg ADC_AWDG_CHANNEL_0
* @arg ...
* @arg ADC_AWDG_CHANNEL_ALL
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_analog_watchdog_monit_channel(uint32_t channel)
{
MODIFY_REG(ADC->AWDG1CR, ADC_AWDG1CR_AWDG1_CHN, channel);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD>ÿ<EFBFBD><EFBFBD>Ź<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><EFBFBD>ֵ
* @param high_threshold <EFBFBD><EFBFBD>ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΧΪ 0x000~0xFFF
* @param low_threshold <EFBFBD><EFBFBD>ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΧΪ 0x000~0xFFF
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_analog_watchdog_thresholds_config(uint32_t high_threshold, uint32_t low_threshold)
{
MODIFY_REG(ADC->AWDG1TR, (ADC_AWDG1TR_AWDG1_LT | ADC_AWDG1TR_AWDG1_HT), (high_threshold << 16U) | (low_threshold >> 0U));
}
/**
* @brief <EFBFBD><EFBFBD>ȡADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
* @retval ADCת<EFBFBD><EFBFBD>ֵ
*/
__STATIC_INLINE uint16_t std_adc_get_conversion_value(void)
{
return ((uint16_t)(ADC->DR));
}
/**
* @brief ʹ<EFBFBD>ܵ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_low_frequency_trig_enable(void)
{
ADC->CFG2 |= (ADC_CFG2_LFTRG);
}
/**
* @brief <EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_low_frequency_trig_disable(void)
{
ADC->CFG2 &= (~ADC_CFG2_LFTRG);
}
/**
* @brief ADC<EFBFBD>ο<EFBFBD><EFBFBD><EFBFBD>ѹԴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg ADC_REFERENCE_VREFBUF
* @arg ADC_REFERENCE_VREFP
* @arg ADC_REFERENCE_VDDA
* @note VRFEBUF<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>ο<EFBFBD><EFBFBD><EFBFBD>ѹԴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>VREFBUF<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PA0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊģ<EFBFBD><EFBFBD>ģʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1uF+0.1uF<EFBFBD><EFBFBD><EFBFBD><EFBFBD>;
* VREF+<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>ο<EFBFBD><EFBFBD><EFBFBD>ѹԴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PA0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊģ<EFBFBD><EFBFBD>ģʽ;
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_adc_set_reference_source(uint32_t reference_voltage)
{
MODIFY_REG(ADC->CFG2, ADC_CFG2_REF, reference_voltage);
}
/* ADC<44><43>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
void std_adc_init(std_adc_init_t *adc_init_param);
/* ADC<44>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>*/
void std_adc_struct_init(std_adc_init_t *adc_init_struct);
/* ADCȥ<43><C8A5>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
void std_adc_deinit(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* CIU32L051_STD_ADC_H */