CIU32_L051_M307R/drivers/src/drv_common.c

/*
 * @Author: mbw
 * @Date: 2024-08-20 15:51:16
 * @LastEditors: mbw && 1600520629@qq.com
 * @LastEditTime: 2024-09-12 17:14:01
 * @FilePath: \USART1_Interrupt - RT-Thread\drivers\src\drv_common.c
 * @Description: 
 * 
 * Copyright (c) 2024 by ${git_name_email}, All Rights Reserved. 
 */
/************************************************************************************************/
/**
* @file               common.c
* @author             MCU Ecosystem Development Team
* @brief              ͨ<EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD>ֺ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
*
**************************************************************************************************
* @attention
* Copyright (c) CEC Huada Electronic Design Co.,Ltd. All rights reserved.
*
**************************************************************************************************
*/

/*------------------------------------------includes--------------------------------------------*/
#include "drv_common.h"

/*-------------------------------------------functions------------------------------------------*/


/**
* @brief  <EFBFBD><EFBFBD><EFBFBD><EFBFBD>HXTALʱ<EFBFBD>Ӳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param  mode HXTALģʽѡ<EFBFBD><EFBFBD>
*             @arg RCC_HXTAL_ON<EFBFBD><EFBFBD>    ʹ<EFBFBD>ܾ<EFBFBD><EFBFBD><EFBFBD>ģʽ
*             @arg RCC_HXTAL_BYPASS<EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD><EFBFBD>ⲿʱ<EFBFBD><EFBFBD>ģʽ
* @param  hxtal_drv HXTAL<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*             @arg RCC_HXTAL_DRIVE_LEVEL0
*             @arg RCC_HXTAL_DRIVE_LEVEL1
*             @arg RCC_HXTAL_DRIVE_LEVEL2
*             @arg RCC_HXTAL_DRIVE_LEVEL3
* @note   <EFBFBD><EFBFBD>HXTAL<EFBFBD><EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HXTALʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ز<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>轫<EFBFBD><EFBFBD>ʱ<EFBFBD>ӽ<EFBFBD>ֹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>á<EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
void bsp_rcc_hxtal_config(uint32_t mode, uint32_t hxtal_drv)
{   
    if (mode == RCC_HXTAL_ON)
    {        
        /* <20><><EFBFBD><EFBFBD>HXTAL<41><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
        std_rcc_hxtal_drive_config(hxtal_drv);
    }
    
    /* ʹ<><CAB9>HXTAL */
    std_rcc_hxtal_enable(mode);
    
    /* <20>ȴ<EFBFBD>HXTALʱ<4C><CAB1><EFBFBD>ȶ<EFBFBD> */
    while(!std_rcc_get_hxtal_ready());
}

/**
* @brief  NMI<EFBFBD>жϷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
void NMI_Handler(void)
{    
    /* <20><><EFBFBD><EFBFBD>HXTAL CSS<53><53>־ */
    std_rcc_clear_flag(RCC_CLEAR_HXTALCSS);
    
    /* <20>л<EFBFBD>ϵͳʱ<CDB3><CAB1>ΪRCH 2<><32>Ƶ(8MHz) */
    
    /* <20>û<EFBFBD><C3BB>ɸ<EFBFBD><C9B8><EFBFBD>ʵ<EFBFBD><CAB5>Ӧ<EFBFBD>ã<EFBFBD>ʵ<EFBFBD><CAB5>HXTAL CSS<53>жϴ<D0B6><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
    
}

/**
* @brief  ϵͳʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
void system_clock_config(void)
{
    /* <20><><EFBFBD><EFBFBD>Flash<73><68><EFBFBD><EFBFBD><EFBFBD>ʵȴ<CAB5>ʱ<EFBFBD><CAB1> */
    std_flash_set_latency(FLASH_LATENCY_2CLK);

  /* <20><><EFBFBD><EFBFBD>HXTALΪ<4C><CEAA><EFBFBD><EFBFBD>ģʽ */
    bsp_rcc_hxtal_config(RCC_HXTAL_ON, RCC_HXTAL_DRIVE_LEVEL1);

    /* <20><><EFBFBD><EFBFBD>PLL<4C><4C><EFBFBD>ز<EFBFBD><D8B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9> */
    std_rcc_pll_config(RCC_PLLSRC_HXTAL, RCC_PLLM_MUL4, RCC_PLLN_DIV1, RCC_PLL_DIV1);//32MHZ
    std_rcc_pll_enable();
    while(!std_rcc_get_pll_ready());
    
    std_rcc_pll_output_enable();

    /* <20><><EFBFBD><EFBFBD>ϵͳʱ<CDB3><CAB1>ԴΪPLL */
    std_rcc_set_sysclk_source(RCC_SYSCLK_SRC_PLLCLK);
    while(std_rcc_get_sysclk_source() != RCC_SYSCLK_SRC_STATUS_PLLCLK);

    /* <20><><EFBFBD><EFBFBD>AHB<48><42>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> */
    std_rcc_set_ahbdiv(RCC_HCLK_DIV1);
    
    /* <20><><EFBFBD><EFBFBD>APB1<42><31>APB2<42><32>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> */
    std_rcc_set_apb1div(RCC_PCLK1_DIV1);
    std_rcc_set_apb2div(RCC_PCLK2_DIV1);
    
    SystemCoreClockUpdate();
}