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CIU32_L051_M307R
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CIU32_L051_M307R/Peripheral/CIU32L051_Lib/Include/ciu32l051_std_rcc.h

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移植了RTThread和RTT打印，并完成了串口的DMA中断发送，和串口空闲中断+DMA接收，测试通过
2024-08-22 16:24:54 +08:00
/************************************************************************************************/
/**
* @file ciu32l051_std_rcc.h
* @author MCU Ecosystem Development Team
* @brief RCC STD<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD>ṩRCC<EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>STD<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Լ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ķ<EFBFBD><EFBFBD>塣
*
*
**************************************************************************************************
* @attention
* Copyright (c) CEC Huada Electronic Design Co.,Ltd. All rights reserved.
*
**************************************************************************************************
*/
/* <20><><EFBFBD><EFBFBD>ͷ<EFBFBD>ļ<EFBFBD><C4BC>ظ<EFBFBD><D8B8><EFBFBD><EFBFBD><EFBFBD> */
#ifndef CIU32L051_STD_RCC_H
#define CIU32L051_STD_RCC_H
/************************************************************************************************/
/**
* @addtogroup CIU32L051_STD_Driver
* @{
*/
/**
* @defgroup RCC RCC
* @brief <EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>ʱ<EFBFBD>ӿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>STD<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @{
*/
/************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------includes--------------------------------------------*/
#include "ciu32l051_std_common.h"
/*--------------------------------------------define--------------------------------------------*/
/************************************************************************************************/
/**
* @defgroup RCC_Constants RCC Constants
* @brief RCC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>弰<EFBFBD>궨<EFBFBD><EFBFBD>
* @{
*
*/
/************************************************************************************************/
/* HXTAL<41><4C><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_HXTAL_ON (0x00000001UL) /**< HXTALʱ<4C>ӿ<EFBFBD><D3BF><EFBFBD> */
#define RCC_HXTAL_BYPASS (0x00000002UL) /**< HXTALΪ<4C>ⲿʱ<E2B2BF><CAB1>ģʽ */
/* LXTAL<41><4C><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_LXTAL_ON (0x00000001UL) /**< LXTALʱ<4C>ӿ<EFBFBD><D3BF><EFBFBD> */
/* RCH<43><48>Ƶϵ<C6B5><CFB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_RCH_DIV1 RCC_CSR1_RCHDIV_1 /**< RCHʱ<48>Ӳ<EFBFBD><D3B2><EFBFBD>Ƶ */
#define RCC_RCH_DIV2 RCC_CSR1_RCHDIV_2 /**< RCHʱ<48>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 2 */
#define RCC_RCH_DIV4 RCC_CSR1_RCHDIV_4 /**< RCHʱ<48>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 4 */
#define RCC_RCH_DIV8 RCC_CSR1_RCHDIV_8 /**< RCHʱ<48>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 8 */
/* HXTAL<41><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_HXTAL_DRIVE_LEVEL0 RCC_CSR1_HXTAL_DRV_0 /**< <20>͵<EFBFBD><CDB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_HXTAL_DRIVE_LEVEL1 RCC_CSR1_HXTAL_DRV_1 /**< <20>е͵<D0B5><CDB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_HXTAL_DRIVE_LEVEL2 RCC_CSR1_HXTAL_DRV_2 /**< <20>иߵ<D0B8><DFB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_HXTAL_DRIVE_LEVEL3 RCC_CSR1_HXTAL_DRV_3 /**< <20>ߵ<EFBFBD><DFB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/* HXTALʱ<4C><CAB1><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_HXTAL_STAB_SEL_256 (0x00000000UL) /**< HXTALʱ<4C><CAB1><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>Ϊ256<35><36>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_HXTAL_STAB_SEL_1024 (0x1UL << RCC_STABC_HXTAL_STAB_SEL_POS) /**< HXTALʱ<4C><CAB1><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>Ϊ1024<32><34>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_HXTAL_STAB_SEL_4096 (0x2UL << RCC_STABC_HXTAL_STAB_SEL_POS) /**< HXTALʱ<4C><CAB1><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>Ϊ4096<39><36>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_HXTAL_STAB_SEL_16384 (0x3UL << RCC_STABC_HXTAL_STAB_SEL_POS) /**< HXTALʱ<4C><CAB1><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>Ϊ16384<38><34>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/* PLL VCO<43><4F>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_PLL_DIV1 RCC_PLLCFG_PLLDIV_1 /**< PLL<4C><4C>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 1 */
#define RCC_PLL_DIV2 RCC_PLLCFG_PLLDIV_2 /**< PLL<4C><4C>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 2 */
#define RCC_PLL_DIV4 RCC_PLLCFG_PLLDIV_4 /**< PLL<4C><4C>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 4 */
#define RCC_PLL_DIV8 RCC_PLLCFG_PLLDIV_8 /**< PLL<4C><4C>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 8 */
/* PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_PLLM_MUL1 (0x01UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 1 */
#define RCC_PLLM_MUL2 (0x02UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 2 */
#define RCC_PLLM_MUL3 (0x03UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 3 */
#define RCC_PLLM_MUL4 (0x04UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 4 */
#define RCC_PLLM_MUL5 (0x05UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 5 */
#define RCC_PLLM_MUL6 (0x06UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 6 */
#define RCC_PLLM_MUL7 (0x07UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 7 */
#define RCC_PLLM_MUL8 (0x08UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 8 */
#define RCC_PLLM_MUL9 (0x09UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 9 */
#define RCC_PLLM_MUL10 (0x0AUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 10 */
#define RCC_PLLM_MUL11 (0x0BUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 11 */
#define RCC_PLLM_MUL12 (0x0CUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 12 */
#define RCC_PLLM_MUL13 (0x0DUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 13 */
#define RCC_PLLM_MUL14 (0x0EUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 14 */
#define RCC_PLLM_MUL15 (0x0FUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 15 */
#define RCC_PLLM_MUL16 (0x10UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 16 */
#define RCC_PLLM_MUL17 (0x11UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 17 */
#define RCC_PLLM_MUL18 (0x12UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 18 */
#define RCC_PLLM_MUL19 (0x13UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 19 */
#define RCC_PLLM_MUL20 (0x14UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 20 */
#define RCC_PLLM_MUL21 (0x15UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 21 */
#define RCC_PLLM_MUL22 (0x16UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 22 */
#define RCC_PLLM_MUL23 (0x17UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 23 */
#define RCC_PLLM_MUL24 (0x18UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 24 */
#define RCC_PLLM_MUL25 (0x19UL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 25 */
#define RCC_PLLM_MUL26 (0x1AUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 26 */
#define RCC_PLLM_MUL27 (0x1BUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 27 */
#define RCC_PLLM_MUL28 (0x1CUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 28 */
#define RCC_PLLM_MUL29 (0x1DUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 29 */
#define RCC_PLLM_MUL30 (0x1EUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 30 */
#define RCC_PLLM_MUL31 (0x1FUL << RCC_PLLCFG_PLLM_POS) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 31 */
#define RCC_PLLM_MUL32 (0x00000000UL) /**< PLLM<4C><4D>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 32 */
/* PLLN<4C><4E>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_PLLN_DIV1 (0x1UL << RCC_PLLCFG_PLLN_POS) /**< PLLN<4C><4E>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 1 */
#define RCC_PLLN_DIV2 (0x2UL << RCC_PLLCFG_PLLN_POS) /**< PLLN<4C><4E>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 2 */
#define RCC_PLLN_DIV3 (0x3UL << RCC_PLLCFG_PLLN_POS) /**< PLLN<4C><4E>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 3 */
#define RCC_PLLN_DIV4 (0x4UL << RCC_PLLCFG_PLLN_POS) /**< PLLN<4C><4E>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 4 */
#define RCC_PLLN_DIV5 (0x5UL << RCC_PLLCFG_PLLN_POS) /**< PLLN<4C><4E>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 5 */
#define RCC_PLLN_DIV6 (0x6UL << RCC_PLLCFG_PLLN_POS) /**< PLLN<4C><4E>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 6 */
#define RCC_PLLN_DIV7 (0x7UL << RCC_PLLCFG_PLLN_POS) /**< PLLN<4C><4E>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 7 */
#define RCC_PLLN_DIV8 (0x00000000UL) /**< PLLN<4C><4E>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 8 */
/* PLLʱ<4C><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD> */
#define RCC_PLLSRC_RCH RCC_PLLCFG_PLLSRC_RCH /**< RCHʱ<48><CAB1><EFBFBD><EFBFBD>ΪPLL<4C><4C>ʱ<EFBFBD><CAB1>Դ */
#define RCC_PLLSRC_HXTAL RCC_PLLCFG_PLLSRC_HXTAL /**< HXTAL<41><4C>ΪPLL<4C><4C>ʱ<EFBFBD><CAB1>Դ */
/* ϵͳʱ<CDB3><CAB1>Դѡ<D4B4><D1A1> */
#define RCC_SYSCLK_SRC_RCHSYS RCC_CFG_SYSW_RCHSYS /**< ѡ<><D1A1>RCHSYS<59><53>Ϊϵͳʱ<CDB3><CAB1>Դ */
#define RCC_SYSCLK_SRC_HXTAL RCC_CFG_SYSW_HXTAL /**< ѡ<><D1A1>HXTAL<41><4C>Ϊϵͳʱ<CDB3><CAB1>Դ */
#define RCC_SYSCLK_SRC_PLLCLK RCC_CFG_SYSW_PLL /**< ѡ<><D1A1>PLL<4C><4C>Ϊϵͳʱ<CDB3><CAB1>Դ */
#define RCC_SYSCLK_SRC_RCL RCC_CFG_SYSW_RCL /**< ѡ<><D1A1>RCL<43><4C>Ϊϵͳʱ<CDB3><CAB1>Դ */
#define RCC_SYSCLK_SRC_LXTAL RCC_CFG_SYSW_LXTAL /**< ѡ<><D1A1>LXTAL<41><4C>Ϊϵͳʱ<CDB3><CAB1>Դ */
/* ϵͳʱ<CDB3><CAB1>Դ״̬<D7B4><CCAC><EFBFBD><EFBFBD> */
#define RCC_SYSCLK_SRC_STATUS_RCHSYS RCC_CFG_SYSWS_RCHSYS /**< ϵͳʱ<CDB3><CAB1>ΪRCHSYS */
#define RCC_SYSCLK_SRC_STATUS_HXTAL RCC_CFG_SYSWS_HXTAL /**< ϵͳʱ<CDB3><CAB1>ΪHXTAL */
#define RCC_SYSCLK_SRC_STATUS_PLLCLK RCC_CFG_SYSWS_PLL /**< ϵͳʱ<CDB3><CAB1>ΪPLL */
#define RCC_SYSCLK_SRC_STATUS_RCL RCC_CFG_SYSWS_RCL /**< ϵͳʱ<CDB3><CAB1>ΪRCL */
#define RCC_SYSCLK_SRC_STATUS_LXTAL RCC_CFG_SYSWS_LXTAL /**< ϵͳʱ<CDB3><CAB1>ΪLXTAL */
/* AHBʱ<42>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_HCLK_DIV1 RCC_CFG_HPRE_1 /**< HCLK<4C><4B><EFBFBD><EFBFBD>Ƶ */
#define RCC_HCLK_DIV2 RCC_CFG_HPRE_2 /**< HCLK<4C><4B>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 2 */
#define RCC_HCLK_DIV4 RCC_CFG_HPRE_4 /**< HCLK<4C><4B>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 4 */
#define RCC_HCLK_DIV8 RCC_CFG_HPRE_8 /**< HCLK<4C><4B>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 8 */
#define RCC_HCLK_DIV16 RCC_CFG_HPRE_16 /**< HCLK<4C><4B>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 16 */
#define RCC_HCLK_DIV32 RCC_CFG_HPRE_32 /**< HCLK<4C><4B>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 32 */
#define RCC_HCLK_DIV64 RCC_CFG_HPRE_64 /**< HCLK<4C><4B>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 64 */
#define RCC_HCLK_DIV128 RCC_CFG_HPRE_128 /**< HCLK<4C><4B>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 128 */
/* APB1ʱ<31>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_PCLK1_DIV1 RCC_CFG_P1PRE_1 /**< APB1<42><31><EFBFBD><EFBFBD>ʱ<EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD>Ƶ */
#define RCC_PCLK1_DIV2 RCC_CFG_P1PRE_2 /**< APB1<42><31><EFBFBD><EFBFBD>ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 2 */
#define RCC_PCLK1_DIV4 RCC_CFG_P1PRE_4 /**< APB1<42><31><EFBFBD><EFBFBD>ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 4 */
#define RCC_PCLK1_DIV8 RCC_CFG_P1PRE_8 /**< APB1<42><31><EFBFBD><EFBFBD>ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 8 */
#define RCC_PCLK1_DIV16 RCC_CFG_P1PRE_16 /**< APB1<42><31><EFBFBD><EFBFBD>ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 16 */
/* APB2ʱ<32>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_PCLK2_DIV1 RCC_CFG_P2PRE_1 /**< APB2<42><32><EFBFBD><EFBFBD>ʱ<EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD>Ƶ */
#define RCC_PCLK2_DIV2 RCC_CFG_P2PRE_2 /**< APB2<42><32><EFBFBD><EFBFBD>ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 2 */
#define RCC_PCLK2_DIV4 RCC_CFG_P2PRE_4 /**< APB2<42><32><EFBFBD><EFBFBD>ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 4 */
#define RCC_PCLK2_DIV8 RCC_CFG_P2PRE_8 /**< APB2<42><32><EFBFBD><EFBFBD>ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 8 */
#define RCC_PCLK2_DIV16 RCC_CFG_P2PRE_16 /**< APB2<42><32><EFBFBD><EFBFBD>ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 16 */
/* MCOʱ<4F><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_MCO_SRC_DISABLE RCC_CFG_MCOSEL_DISABLE /**< MCO<43><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч */
#define RCC_MCO_SRC_SYSCLK RCC_CFG_MCOSEL_SYSCLK /**< MCOѡ<4F><D1A1>SYSCLK<4C><4B><EFBFBD><EFBFBD> */
#define RCC_MCO_SRC_RCH RCC_CFG_MCOSEL_RCH /**< MCOѡ<4F><D1A1>RCH<43><48><EFBFBD><EFBFBD> */
#define RCC_MCO_SRC_HXTAL RCC_CFG_MCOSEL_HXTAL /**< MCOѡ<4F><D1A1>HXTAL<41><4C><EFBFBD><EFBFBD> */
#define RCC_MCO_SRC_PLLCLK RCC_CFG_MCOSEL_PLLCLK /**< MCOѡ<4F><D1A1>PLLCLK<4C><4B><EFBFBD><EFBFBD> */
#define RCC_MCO_SRC_RCL RCC_CFG_MCOSEL_RCL /**< MCOѡ<4F><D1A1>RCL<43><4C><EFBFBD><EFBFBD> */
#define RCC_MCO_SRC_LXTAL RCC_CFG_MCOSEL_LXTAL /**< MCOѡ<4F><D1A1>LXTAL<41><4C><EFBFBD><EFBFBD> */
/* MCOʱ<4F>ӷ<EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_MCO_DIV1 RCC_CFG_MCOPRE_DIV1 /**< MCO<43><4F>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 1 */
#define RCC_MCO_DIV2 RCC_CFG_MCOPRE_DIV2 /**< MCO<43><4F>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 2 */
#define RCC_MCO_DIV4 RCC_CFG_MCOPRE_DIV4 /**< MCO<43><4F>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 4 */
#define RCC_MCO_DIV8 RCC_CFG_MCOPRE_DIV8 /**< MCO<43><4F>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 8 */
#define RCC_MCO_DIV16 RCC_CFG_MCOPRE_DIV16 /**< MCO<43><4F>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 16 */
#define RCC_MCO_DIV32 RCC_CFG_MCOPRE_DIV32 /**< MCO<43><4F>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 32 */
#define RCC_MCO_DIV64 RCC_CFG_MCOPRE_DIV64 /**< MCO<43><4F>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 64 */
#define RCC_MCO_DIV128 RCC_CFG_MCOPRE_DIV128 /**< MCO<43><4F>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD> = 128 */
/* RCC<43>жϿ<D0B6><CFBF><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD> */
#define RCC_INTERRUPT_RCL_READY RCC_IER_RCL_RDYIE /**< RCL Ready<64><79><EFBFBD>жϿ<D0B6><CFBF><EFBFBD>λ */
#define RCC_INTERRUPT_LXTAL_READY RCC_IER_LXTAL_RDYIE /**< LXTAL Ready<64><79><EFBFBD>жϿ<D0B6><CFBF><EFBFBD>λ */
#define RCC_INTERRUPT_RCH_READY RCC_IER_RCH_RDYIE /**< RCH Ready<64><79><EFBFBD>жϿ<D0B6><CFBF><EFBFBD>λ */
#define RCC_INTERRUPT_HXTAL_READY RCC_IER_HXTAL_RDYIE /**< HXTAL Ready<64><79><EFBFBD>жϿ<D0B6><CFBF><EFBFBD>λ */
#define RCC_INTERRUPT_PLL_READY RCC_IER_PLL_RDYIE /**< PLL Ready<64><79><EFBFBD>жϿ<D0B6><CFBF><EFBFBD>λ */
/* RCC<43>жϱ<D0B6>־λ<D6BE><CEBB><EFBFBD><EFBFBD> */
#define RCC_FLAG_RCL_READY RCC_ISR_RCL_RDYF /**< RCL Ready<64><79><EFBFBD>жϱ<D0B6>־λ */
#define RCC_FLAG_LXTAL_READY RCC_ISR_LXTAL_RDYF /**< LXTAL Ready<64><79><EFBFBD>жϱ<D0B6>־λ */
#define RCC_FLAG_RCH_READY RCC_ISR_RCH_RDYF /**< RCH Ready<64><79><EFBFBD>жϱ<D0B6>־λ */
#define RCC_FLAG_HXTAL_READY RCC_ISR_HXTAL_RDYF /**< HXTAL Ready<64><79><EFBFBD>жϱ<D0B6>־λ */
#define RCC_FLAG_PLL_READY RCC_ISR_PLL_RDYF /**< PLL Ready<64><79><EFBFBD>жϱ<D0B6>־λ */
#define RCC_FLAG_HXTALCSS RCC_ISR_HXTAL_CSSF /**< HXTAL CSS<53><53><EFBFBD>жϱ<D0B6>־λ */
/* RCC<43><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD> */
#define RCC_CLEAR_RCL_READY RCC_ICR_RCL_RDYC /**< RCL Ready<64><79><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
#define RCC_CLEAR_LXTAL_READY RCC_ICR_LXTAL_RDYC /**< LXTAL Ready<64><79><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
#define RCC_CLEAR_RCH_READY RCC_ICR_RCH_RDYC /**< RCH Ready<64><79><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
#define RCC_CLEAR_HXTAL_READY RCC_ICR_HXTAL_RDYC /**< HXTAL Ready<64><79><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
#define RCC_CLEAR_PLL_READY RCC_ICR_PLL_RDYC /**< PLL Ready<64><79><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
#define RCC_CLEAR_HXTALCSS RCC_ICR_HXTAL_CSSC /**< HXTAL CSS<53><53><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
/* LXTAL<41><4C><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_LXTAL_DRIVE_MODE_NORMAL (0x00000000UL) /**< LXTAL<41><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>ͨ<EFBFBD><CDA8> */
#define RCC_LXTAL_DRIVE_MODE_ENHANCE (0x1UL << RCC_AWCR_LXTAL_DRV_MODE_POS) /**< LXTAL<41><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>ǿ<EFBFBD><C7BF> */
/* LXTAL<41><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ö<EFBFBD><C3B6><EFBFBD> */
#define RCC_LXTAL_DRIVE_LEVEL0 RCC_AWCR_LXTAL_DRV_0 /**< LXTAL<41><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_LXTAL_DRIVE_LEVEL1 RCC_AWCR_LXTAL_DRV_1 /**< LXTAL<41>е<EFBFBD><D0B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_LXTAL_DRIVE_LEVEL2 RCC_AWCR_LXTAL_DRV_2 /**< LXTAL<41>и<EFBFBD><D0B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_LXTAL_DRIVE_LEVEL3 RCC_AWCR_LXTAL_DRV_3 /**< LXTAL<41><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/* LXTALʱ<4C><CAB1><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_LXTAL_STAB_SEL_256 (0x00000000UL) /**< LXTALʱ<4C><CAB1><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>Ϊ256<35><36>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_LXTAL_STAB_SEL_1024 (0x1UL << RCC_AWCR_LXTAL_STAB_SEL_POS) /**< LXTALʱ<4C><CAB1><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>Ϊ1024<32><34>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_LXTAL_STAB_SEL_4096 (0x2UL << RCC_AWCR_LXTAL_STAB_SEL_POS) /**< LXTALʱ<4C><CAB1><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>Ϊ4096<39><36>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_LXTAL_STAB_SEL_16384 (0x3UL << RCC_AWCR_LXTAL_STAB_SEL_POS) /**< LXTALʱ<4C><CAB1><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>Ϊ16384<38><34>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/* IO<49>˿<EFBFBD>ʱ<EFBFBD><CAB1>ѡ<EFBFBD><D1A1> */
#define RCC_PERIPH_CLK_GPIOA RCC_IOPEN_GPIOAEN /**< GPIOA ʱ<>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_GPIOB RCC_IOPEN_GPIOBEN /**< GPIOB ʱ<>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_GPIOC RCC_IOPEN_GPIOCEN /**< GPIOC ʱ<>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_GPIOD RCC_IOPEN_GPIODEN /**< GPIOD ʱ<>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_GPIOF RCC_IOPEN_GPIOFEN /**< GPIOF ʱ<>ӿ<EFBFBD><D3BF><EFBFBD>λ */
/* IO<49>˿ڸ<CBBF>λѡ<CEBB><D1A1> */
#define RCC_PERIPH_RESET_GPIO_ALL RCC_IOPRST_GPIOA_RST | RCC_IOPRST_GPIOB_RST \
| RCC_IOPRST_GPIOC_RST \
| RCC_IOPRST_GPIOD_RST \
| RCC_IOPRST_GPIOF_RST /**< GPIO<49><4F><EFBFBD>ж˿ڸ<CBBF>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_GPIOA RCC_IOPRST_GPIOA_RST /**< GPIOA<4F>˿ڸ<CBBF>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_GPIOB RCC_IOPRST_GPIOB_RST /**< GPIOB<4F>˿ڸ<CBBF>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_GPIOC RCC_IOPRST_GPIOC_RST /**< GPIOC<4F>˿ڸ<CBBF>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_GPIOD RCC_IOPRST_GPIOD_RST /**< GPIOD<4F>˿ڸ<CBBF>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_GPIOF RCC_IOPRST_GPIOF_RST /**< GPIOF<4F>˿ڸ<CBBF>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
/* AHB<48><42><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ѡ<EFBFBD><D1A1> */
#define RCC_PERIPH_CLK_DMA RCC_AHBEN_DMAEN /**< AHB<48><42><EFBFBD><EFBFBD>DMAʱ<41>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_FLASH RCC_AHBEN_FLASHEN /**< AHB<48><42><EFBFBD><EFBFBD>Flashʱ<68>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_CRC RCC_AHBEN_CRCEN /**< AHB<48><42><EFBFBD><EFBFBD>CRCʱ<43>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_AES RCC_AHBEN_AESEN /**< AHB<48><42><EFBFBD><EFBFBD>AESʱ<53>ӿ<EFBFBD><D3BF><EFBFBD>λ */
/* AHB<48><42><EFBFBD>踴λѡ<CEBB><D1A1> */
#define RCC_PERIPH_RESET_AHB RCC_AHBRST_DMA_RST | RCC_AHBRST_CRC_RST \
| RCC_AHBRST_AES_RST /**< AHB<48><42><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>踴λ<E8B8B4><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_DMA RCC_AHBRST_DMA_RST /**< AHB<48><42><EFBFBD><EFBFBD>DMA<4D><41>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_CRC RCC_AHBRST_CRC_RST /**< AHB<48><42><EFBFBD><EFBFBD>CRC<52><43>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_AES RCC_AHBRST_AES_RST /**< AHB<48><42><EFBFBD><EFBFBD>AES<45><53>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
/* APB1<42><31><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ѡ<EFBFBD><D1A1> */
#define RCC_PERIPH_CLK_TIM3 RCC_APB1EN_TIM3EN /**< APB1<42><31><EFBFBD><EFBFBD>TIM3ʱ<33>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_TIM4 RCC_APB1EN_TIM4EN /**< APB1<42><31><EFBFBD><EFBFBD>TIM4ʱ<34>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_TIM5 RCC_APB1EN_TIM5EN /**< APB1<42><31><EFBFBD><EFBFBD>TIM5ʱ<35>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_TIM8 RCC_APB1EN_TIM8EN /**< APB1<42><31><EFBFBD><EFBFBD>TIM8ʱ<38>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_LCD RCC_APB1EN_LCDEN /**< APB1<42><31><EFBFBD><EFBFBD>LCDʱ<44>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_RTC RCC_APB1EN_RTCAPBEN /**< APB1<42><31><EFBFBD><EFBFBD>RTCʱ<43>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_WWDG RCC_APB1EN_WWDGEN /**< APB1<42><31><EFBFBD><EFBFBD>WWDGSHʱ<48>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_SPI2 RCC_APB1EN_SPI2EN /**< APB1<42><31><EFBFBD><EFBFBD>SPI2ʱ<32>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_UART2 RCC_APB1EN_UART2EN /**< APB1<42><31><EFBFBD><EFBFBD>UART2ʱ<32>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_UART3 RCC_APB1EN_UART3EN /**< APB1<42><31><EFBFBD><EFBFBD>UART3ʱ<33>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_UART4 RCC_APB1EN_UART4EN /**< APB1<42><31><EFBFBD><EFBFBD>UART4ʱ<34>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_LPUART1 RCC_APB1EN_LPUART1EN /**< APB1<42><31><EFBFBD><EFBFBD>LPUART1ʱ<31>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_LPUART2 RCC_APB1EN_LPUART2EN /**< APB1<42><31><EFBFBD><EFBFBD>LPUART2ʱ<32>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_I2C1 RCC_APB1EN_I2C1EN /**< APB1<42><31><EFBFBD><EFBFBD>I2C1ʱ<31>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_PMU RCC_APB1EN_PMUEN /**< APB1<42><31><EFBFBD><EFBFBD>PMUʱ<55>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_LPTIM1 RCC_APB1EN_LPTIM1EN /**< APB1<42><31><EFBFBD><EFBFBD>LPTIM1ʱ<31>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_LPTIM2 RCC_APB1EN_LPTIM2EN /**< APB1<42><31><EFBFBD><EFBFBD>LPTIM2ʱ<32>ӿ<EFBFBD><D3BF><EFBFBD>λ */
/* APB1<42><31><EFBFBD>踴λѡ<CEBB><D1A1> */
#define RCC_PERIPH_RESET_APB1 RCC_APB1RST_TIM3_RST | RCC_APB1RST_TIM4_RST \
| RCC_APB1RST_TIM5_RST \
| RCC_APB1RST_TIM8_RST \
| RCC_APB1RST_LCD_RST \
| RCC_APB1RST_SPI2_RST \
| RCC_APB1RST_UART2_RST \
| RCC_APB1RST_UART3_RST \
| RCC_APB1RST_UART4_RST \
| RCC_APB1RST_LPUART1_RST \
| RCC_APB1RST_LPUART2_RST \
| RCC_APB1RST_I2C1_RST \
| RCC_APB1RST_LPTIM1_RST \
| RCC_APB1RST_LPTIM2_RST /**< APB1<42><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>踴λ<E8B8B4><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_TIM3 RCC_APB1RST_TIM3_RST /**< APB1<42><31><EFBFBD><EFBFBD>TIM3<4D><33>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_TIM4 RCC_APB1RST_TIM4_RST /**< APB1<42><31><EFBFBD><EFBFBD>TIM4<4D><34>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_TIM5 RCC_APB1RST_TIM5_RST /**< APB1<42><31><EFBFBD><EFBFBD>TIM5<4D><35>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_TIM8 RCC_APB1RST_TIM8_RST /**< APB1<42><31><EFBFBD><EFBFBD>TIM8<4D><38>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_LCD RCC_APB1RST_LCD_RST /**< APB1<42><31><EFBFBD><EFBFBD>LCD<43><44>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_SPI2 RCC_APB1RST_SPI2_RST /**< APB1<42><31><EFBFBD><EFBFBD>SPI2ʱ<32><CAB1>λ<EFBFBD><CEBB>λ */
#define RCC_PERIPH_RESET_UART2 RCC_APB1RST_UART2_RST /**< APB1<42><31><EFBFBD><EFBFBD>UART2<54><32>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_UART3 RCC_APB1RST_UART3_RST /**< APB1<42><31><EFBFBD><EFBFBD>UART3<54><33>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_UART4 RCC_APB1RST_UART4_RST /**< APB1<42><31><EFBFBD><EFBFBD>UART4<54><34>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_LPUART1 RCC_APB1RST_LPUART1_RST /**< APB1<42><31><EFBFBD><EFBFBD>LPUART1<54><31>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_LPUART2 RCC_APB1RST_LPUART2_RST /**< APB1<42><31><EFBFBD><EFBFBD>LPUART2<54><32>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_I2C1 RCC_APB1RST_I2C1_RST /**< APB1<42><31><EFBFBD><EFBFBD>I2C1<43><31>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_LPTIM1 RCC_APB1RST_LPTIM1_RST /**< APB1<42><31><EFBFBD><EFBFBD>LPTIM1<4D><31>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_LPTIM2 RCC_APB1RST_LPTIM2_RST /**< APB1<42><31><EFBFBD><EFBFBD>LPTIM2<4D><32>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
/* APB2<42><32><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ѡ<EFBFBD><D1A1> */
#define RCC_PERIPH_CLK_SYSCFG RCC_APB2EN_SYSCFGEN /**< APB2<42><32><EFBFBD><EFBFBD>SYSCFGʱ<47>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_TRNG RCC_APB2EN_TRNGEN /**< APB2<42><32><EFBFBD><EFBFBD>TRNGʱ<47>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_SPI1 RCC_APB2EN_SPI1EN /**< APB2<42><32><EFBFBD><EFBFBD>SPI1ʱ<31>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_USART1 RCC_APB2EN_USART1EN /**< APB2<42><32><EFBFBD><EFBFBD>USART1ʱ<31>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_ADC RCC_APB2EN_ADCEN /**< APB2<42><32><EFBFBD><EFBFBD>ADCʱ<43>ӿ<EFBFBD><D3BF><EFBFBD>λ */
#define RCC_PERIPH_CLK_DBG RCC_APB2EN_DBGEN /**< APB2<42><32><EFBFBD><EFBFBD>DBGʱ<47>ӿ<EFBFBD><D3BF><EFBFBD>λ */
/* APB2<42><32><EFBFBD>踴λѡ<CEBB><D1A1> */
#define RCC_PERIPH_RESET_APB2 RCC_APB2RST_SYSCFG_RST | RCC_APB2RST_TRNG_RST \
| RCC_APB2RST_SPI1_RST \
| RCC_APB2RST_USART1_RST \
| RCC_APB2RST_ADC_RST \
| RCC_APB2RST_DBG_RST /**< APB2<42><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>踴λ<E8B8B4><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_SYSCFG RCC_APB2RST_SYSCFG_RST /**< APB2<42><32><EFBFBD><EFBFBD>SYSCFG<46><47>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_TRNG RCC_APB2RST_TRNG_RST /**< APB2<42><32><EFBFBD><EFBFBD>TRNGʱ<47><CAB1>λ<EFBFBD><CEBB>λ */
#define RCC_PERIPH_RESET_SPI1 RCC_APB2RST_SPI1_RST /**< APB2<42><32><EFBFBD><EFBFBD>SPI1<49><31>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_USART1 RCC_APB2RST_USART1_RST /**< APB2<42><32><EFBFBD><EFBFBD>USART<52><54>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_ADC RCC_APB2RST_ADC_RST /**< APB2<42><32><EFBFBD><EFBFBD>ADC<44><43>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
#define RCC_PERIPH_RESET_DBG RCC_APB2RST_DBG_RST /**< APB2<42><32><EFBFBD><EFBFBD>DBG<42><47>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>λ */
/* LPUART1<54>첽ʱ<ECB2BD><CAB1>Դѡ<D4B4><D1A1> */
#define RCC_LPUART1_ASYNC_CLK_SRC_PCLK1 RCC_CLKSEL_LPUART1_SEL_PCLK /**< APBʱ<42><CAB1><EFBFBD><EFBFBD>ΪLPUART1<54><31>ʱ<EFBFBD><CAB1> */
#define RCC_LPUART1_ASYNC_CLK_SRC_SYSCLK RCC_CLKSEL_LPUART1_SEL_SYSCLK /**< ϵͳʱ<CDB3><CAB1><EFBFBD><EFBFBD>ΪLPUART1<54><31>ʱ<EFBFBD><CAB1> */
#define RCC_LPUART1_ASYNC_CLK_SRC_RCH RCC_CLKSEL_LPUART1_SEL_RCH /**< RCHʱ<48><CAB1><EFBFBD><EFBFBD>ΪLPUART1<54><31>ʱ<EFBFBD><CAB1> */
#define RCC_LPUART1_ASYNC_CLK_SRC_LXTAL RCC_CLKSEL_LPUART1_SEL_LXTAL /**< LXTALʱ<4C><CAB1><EFBFBD><EFBFBD>ΪLPUART1<54><31>ʱ<EFBFBD><CAB1> */
/* LPUART2<54>첽ʱ<ECB2BD><CAB1>Դѡ<D4B4><D1A1> */
#define RCC_LPUART2_ASYNC_CLK_SRC_PCLK1 RCC_CLKSEL_LPUART2_SEL_PCLK /**< APBʱ<42><CAB1><EFBFBD><EFBFBD>ΪLPUART2<54><32>ʱ<EFBFBD><CAB1> */
#define RCC_LPUART2_ASYNC_CLK_SRC_SYSCLK RCC_CLKSEL_LPUART2_SEL_SYSCLK /**< ϵͳʱ<CDB3><CAB1><EFBFBD><EFBFBD>ΪLPUART2<54><32>ʱ<EFBFBD><CAB1> */
#define RCC_LPUART2_ASYNC_CLK_SRC_RCH RCC_CLKSEL_LPUART2_SEL_RCH /**< RCHʱ<48><CAB1><EFBFBD><EFBFBD>ΪLPUART2<54><32>ʱ<EFBFBD><CAB1> */
#define RCC_LPUART2_ASYNC_CLK_SRC_LXTAL RCC_CLKSEL_LPUART2_SEL_LXTAL /**< LXTALʱ<4C><CAB1><EFBFBD><EFBFBD>ΪLPUART2<54><32>ʱ<EFBFBD><CAB1> */
/* LPTIM1<4D>첽ʱ<ECB2BD><CAB1>Դѡ<D4B4><D1A1> */
#define RCC_LPTIM1_ASYNC_CLK_SRC_PCLK1 RCC_CLKSEL_LPTIM1_SEL_PCLK /**< APB1ʱ<31><CAB1><EFBFBD><EFBFBD>ΪLPTIM1<4D><31>ʱ<EFBFBD><CAB1> */
#define RCC_LPTIM1_ASYNC_CLK_SRC_RCL RCC_CLKSEL_LPTIM1_SEL_RCL /**< RCL<43><4C>ΪLPTIM1<4D><31>ʱ<EFBFBD><CAB1> */
#define RCC_LPTIM1_ASYNC_CLK_SRC_RCH RCC_CLKSEL_LPTIM1_SEL_RCH /**< RCHʱ<48><CAB1><EFBFBD><EFBFBD>ΪLPTIM1<4D><31>ʱ<EFBFBD><CAB1> */
#define RCC_LPTIM1_ASYNC_CLK_SRC_LXTAL RCC_CLKSEL_LPTIM1_SEL_LXTAL /**< LXTALʱ<4C><CAB1><EFBFBD><EFBFBD>ΪLPTIM1<4D><31>ʱ<EFBFBD><CAB1> */
/* LPTIM2<4D>첽ʱ<ECB2BD><CAB1>Դѡ<D4B4><D1A1> */
#define RCC_LPTIM2_ASYNC_CLK_SRC_PCLK1 RCC_CLKSEL_LPTIM2_SEL_PCLK /**< APB1ʱ<31><CAB1><EFBFBD><EFBFBD>ΪLPTIM2<4D><32>ʱ<EFBFBD><CAB1> */
#define RCC_LPTIM2_ASYNC_CLK_SRC_RCL RCC_CLKSEL_LPTIM2_SEL_RCL /**< RCL<43><4C>ΪLPTIM2<4D><32>ʱ<EFBFBD><CAB1> */
#define RCC_LPTIM2_ASYNC_CLK_SRC_RCH RCC_CLKSEL_LPTIM2_SEL_RCH /**< RCHʱ<48><CAB1><EFBFBD><EFBFBD>ΪLPTIM2<4D><32>ʱ<EFBFBD><CAB1> */
#define RCC_LPTIM2_ASYNC_CLK_SRC_LXTAL RCC_CLKSEL_LPTIM2_SEL_LXTAL /**< LXTALʱ<4C><CAB1><EFBFBD><EFBFBD>ΪLPTIM2<4D><32>ʱ<EFBFBD><CAB1> */
/* I2C1<43>첽ʱ<ECB2BD><CAB1>Դѡ<D4B4><D1A1> */
#define RCC_I2C1_ASYNC_CLK_SRC_PCLK1 RCC_CLKSEL_I2C1_SEL_PCLK /**< APBʱ<42><CAB1><EFBFBD><EFBFBD>ΪI2C1<43><31>ʱ<EFBFBD><CAB1> */
#define RCC_I2C1_ASYNC_CLK_SRC_SYSCLK RCC_CLKSEL_I2C1_SEL_SYSCLK /**< ϵͳʱ<CDB3><CAB1><EFBFBD><EFBFBD>ΪI2C1<43><31>ʱ<EFBFBD><CAB1> */
#define RCC_I2C1_ASYNC_CLK_SRC_RCH RCC_CLKSEL_I2C1_SEL_RCH /**< RCHʱ<48><CAB1><EFBFBD><EFBFBD>ΪI2C1<43><31>ʱ<EFBFBD><CAB1> */
/* ADC<44>첽ʱ<ECB2BD><CAB1>Դѡ<D4B4><D1A1> */
#define RCC_ADC_ASYNC_CLK_SRC_SYSCLK RCC_CLKSEL_ADC_SEL_SYSCLK /**< ϵͳʱ<CDB3><CAB1><EFBFBD><EFBFBD>ΪADCʱ<43><CAB1> */
#define RCC_ADC_ASYNC_CLK_SRC_SYS_DIV2 RCC_CLKSEL_ADC_SEL_SYSCLK_DIV2 /**< ϵͳʱ<CDB3><CAB1>2<EFBFBD><32>Ƶ<EFBFBD><C6B5>ΪADCʱ<43><CAB1> */
#define RCC_ADC_ASYNC_CLK_SRC_SYS_DIV4 RCC_CLKSEL_ADC_SEL_SYSCLK_DIV4 /**< ϵͳʱ<CDB3><CAB1>4<EFBFBD><34>Ƶ<EFBFBD><C6B5>ΪADCʱ<43><CAB1> */
#define RCC_ADC_ASYNC_CLK_SRC_RCH RCC_CLKSEL_ADC_SEL_RCH /**< RCHʱ<48><CAB1><EFBFBD><EFBFBD>ΪADCʱ<43><CAB1> */
/* RTC<54><43>LCD<43>첽ʱ<ECB2BD><CAB1>Դѡ<D4B4><D1A1> */
#define RCC_RTC_ASYNC_CLK_SRC_NONE RCC_AWCR_RTCSEL_NONE /**< RTC<54><43>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define RCC_RTC_ASYNC_CLK_SRC_LXTAL RCC_AWCR_RTCSEL_LXTAL /**< RTCʱ<43><CAB1>ΪLXTAL */
#define RCC_RTC_ASYNC_CLK_SRC_RCL RCC_AWCR_RTCSEL_RCL /**< RTCʱ<43><CAB1>ΪRCL */
/* <20><>λ<EFBFBD><CEBB>־<EFBFBD><D6BE><EFBFBD><EFBFBD> */
#define RCC_RESET_FLAG_LOCKUP RCC_CSR2_LOCKUP_RSTF /**< LOCKUP<55><50>λ<EFBFBD><CEBB>־ */
#define RCC_RESET_FLAG_OBL RCC_CSR2_OBL_RSTF /**< ѡ<><D1A1><EFBFBD>ֽڼ<D6BD><DABC>ظ<EFBFBD>λ<EFBFBD><CEBB>־ */
#define RCC_RESET_FLAG_NRST RCC_CSR2_NRST_RSTF /**< NRST<53><54><EFBFBD>Ÿ<EFBFBD>λ<EFBFBD><CEBB>־ */
#define RCC_RESET_FLAG_PMU RCC_CSR2_PMU_RSTF /**< POR/PDR<44><52>BOR<4F><52>λ<EFBFBD><CEBB>־ */
#define RCC_RESET_FLAG_SW RCC_CSR2_SW_RSTF /**< <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>־ */
#define RCC_RESET_FLAG_IWDG RCC_CSR2_IWDG_RSTF /**< IWDG<44><47>λ<EFBFBD><CEBB>־ */
#define RCC_RESET_FLAG_WWDG RCC_CSR2_WWDG_RSTF /**< WWDG<44><47>λ<EFBFBD><CEBB>־ */
#define RCC_RESET_FLAG_LPM RCC_CSR2_LPM_RSTF /**< <20>͹<EFBFBD><CDB9>ĸ<EFBFBD>λ<EFBFBD><CEBB>־ */
#define RCC_RESET_FLAG_ALL (0xFFUL<<RCC_CSR2_LOCKUP_RSTF_POS) /**< <20><><EFBFBD>и<EFBFBD>λ<EFBFBD><CEBB>־ */
/**
* @}
*/
/*-------------------------------------------functions------------------------------------------*/
/************************************************************************************************/
/**
* @defgroup RCC_External_Functions RCC External Functions
* @brief RCC<EFBFBD><EFBFBD><EFBFBD>⺯<EFBFBD><EFBFBD>
* @{
*
*/
/************************************************************************************************/
/**
* @brief ʹ<EFBFBD><EFBFBD>RCHʱ<EFBFBD><EFBFBD>
* @note ʹ<EFBFBD><EFBFBD>RCH<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD>ȴ<EFBFBD>RCHRDY<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ø<EFBFBD>ʱ<EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_rch_enable(void)
{
RCC->CSR1 |= RCC_CSR1_RCHON;
}
/**
* @brief <EFBFBD>ر<EFBFBD>RCHʱ<EFBFBD><EFBFBD>
* @note <EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCHΪϵͳʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>䲻<EFBFBD>ܱ<EFBFBD>ֹͣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>û<EFBFBD>Ӧ<EFBFBD>Ƚ<EFBFBD>ϵͳʱ<EFBFBD><EFBFBD>Դ<EFBFBD>л<EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӣ<EFBFBD><EFBFBD>ٹرո<EFBFBD>ʱ<EFBFBD><EFBFBD>Դ
* @note <EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD>RCHʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD>RCHRDY<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_rch_disable(void)
{
RCC->CSR1 &= (~RCC_CSR1_RCHON);
}
/**
* @brief <EFBFBD><EFBFBD>ȡRCH ready<EFBFBD><EFBFBD>־
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>жϽ<EFBFBD><EFBFBD><EFBFBD>
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾRCH ready<EFBFBD><EFBFBD>λ
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾRCH readyδ<EFBFBD><EFBFBD>λ
*/
__STATIC_INLINE bool std_rcc_get_rch_ready(void)
{
return((RCC->CSR1 & RCC_CSR1_RCHRDY) == RCC_CSR1_RCHRDY);
}
/**
* @brief RCH<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param rchdiv <EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCH<EFBFBD>ķ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_RCH_DIV1<EFBFBD><EFBFBD>RCHʱ<EFBFBD><EFBFBD>1<EFBFBD><EFBFBD>Ƶ
* @arg RCC_RCH_DIV2<EFBFBD><EFBFBD>RCHʱ<EFBFBD><EFBFBD>2<EFBFBD><EFBFBD>Ƶ
* @arg RCC_RCH_DIV4<EFBFBD><EFBFBD>RCHʱ<EFBFBD><EFBFBD>4<EFBFBD><EFBFBD>Ƶ
* @arg RCC_RCH_DIV8<EFBFBD><EFBFBD>RCHʱ<EFBFBD><EFBFBD>8<EFBFBD><EFBFBD>Ƶ
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_rchdiv(uint32_t rchdiv)
{
MODIFY_REG(RCC->CSR1, RCC_CSR1_RCHDIV, (rchdiv));
}
/**
* @brief <EFBFBD><EFBFBD>ȡRCH<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval uint32_t RCH<EFBFBD>ķ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_RCH_DIV1<EFBFBD><EFBFBD>RCHʱ<EFBFBD><EFBFBD>1<EFBFBD><EFBFBD>Ƶ
* @arg RCC_RCH_DIV2<EFBFBD><EFBFBD>RCHʱ<EFBFBD><EFBFBD>2<EFBFBD><EFBFBD>Ƶ
* @arg RCC_RCH_DIV4<EFBFBD><EFBFBD>RCHʱ<EFBFBD><EFBFBD>4<EFBFBD><EFBFBD>Ƶ
* @arg RCC_RCH_DIV8<EFBFBD><EFBFBD>RCHʱ<EFBFBD><EFBFBD>8<EFBFBD><EFBFBD>Ƶ
*/
__STATIC_INLINE uint32_t std_rcc_get_rchdiv(void)
{
return(RCC->CSR1 & RCC_CSR1_RCHDIV);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>PLLʱ<EFBFBD>Ӳ<EFBFBD><EFBFBD><EFBFBD>
* @param pllsource PLLʱ<EFBFBD><EFBFBD>Դ
* @arg RCC_PLLSRC_RCH
* @arg RCC_PLLSRC_HXTAL
* @param pllm PLLʱ<EFBFBD>ӱ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>m
* @arg RCC_PLLM_MUL1
* @arg RCC_PLLM_MUL4
* @arg ...
* @arg RCC_PLLM_MUL32
* @param plln PLLʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>n
* @arg RCC_PLLN_DIV1
* @arg RCC_PLLN_DIV2
* @arg ...
* @arg RCC_PLLN_DIV8
* @param plldiv PLL VCO<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_PLL_DIV1
* @arg RCC_PLL_DIV2
* @arg RCC_PLL_DIV4
* @arg RCC_PLL_DIV8
* @note PLL<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ñ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PLLʹ<EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD>һ<EFBFBD><EFBFBD>PLLʹ<EFBFBD>ܺ<EFBFBD><EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܸ<EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_pll_config(uint32_t pllsource, uint32_t pllm, uint32_t plln, uint32_t plldiv)
{
MODIFY_REG(RCC->PLLCFG, RCC_PLLCFG_PLLSRC | RCC_PLLCFG_PLLDIV | RCC_PLLCFG_PLLM | RCC_PLLCFG_PLLN,
pllsource | plldiv | pllm | plln);
}
/**
* @brief <EFBFBD><EFBFBD>ȡPLLʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>Ϣ
* @retval uint32_t PLLʱ<EFBFBD><EFBFBD>Դ
* @arg RCC_PLLSRC_RCH
* @arg RCC_PLLSRC_HXTAL
*/
__STATIC_INLINE uint32_t std_rcc_get_pllsource(void)
{
return(RCC->PLLCFG & RCC_PLLCFG_PLLSRC);
}
/**
* @brief ʹ<EFBFBD><EFBFBD>PLLʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_pll_output_enable(void)
{
RCC->PLLCFG |= RCC_PLLCFG_PLLEN;
}
/**
* @brief <EFBFBD><EFBFBD>ֹPLLʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_pll_output_disable(void)
{
RCC->PLLCFG &= (~RCC_PLLCFG_PLLEN);
}
/**
* @brief ʹ<EFBFBD><EFBFBD>PLLʱ<EFBFBD><EFBFBD>
* @note ʹ<EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD>ȴ<EFBFBD>PLLRDY<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ø<EFBFBD>ʱ<EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_pll_enable(void)
{
RCC->CSR1 |= RCC_CSR1_PLLON;
}
/**
* @brief <EFBFBD>ر<EFBFBD>PLLʱ<EFBFBD><EFBFBD>
* @note <EFBFBD><EFBFBD><EFBFBD><EFBFBD>PLLΪϵͳʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>䲻<EFBFBD>ܱ<EFBFBD>ֹͣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>û<EFBFBD>Ӧ<EFBFBD>Ƚ<EFBFBD>ϵͳʱ<EFBFBD><EFBFBD>Դ<EFBFBD>л<EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӣ<EFBFBD><EFBFBD>ٹرո<EFBFBD>ʱ<EFBFBD><EFBFBD>Դ
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_pll_disable(void)
{
RCC->CSR1 &= (~RCC_CSR1_PLLON);
}
/**
* @brief <EFBFBD><EFBFBD>ȡPLL ready<EFBFBD><EFBFBD>־
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>жϽ<EFBFBD><EFBFBD><EFBFBD>
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾPLL ready<EFBFBD><EFBFBD>λ
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾPLL readyδ<EFBFBD><EFBFBD>λ
*/
__STATIC_INLINE bool std_rcc_get_pll_ready(void)
{
return((RCC->CSR1 & RCC_CSR1_PLLRDY) == RCC_CSR1_PLLRDY);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳʱ<EFBFBD><EFBFBD>Դ
* @param clocksource ϵͳʱ<EFBFBD><EFBFBD>Դ
* @arg RCC_SYSCLK_SRC_RCHSYS
* @arg RCC_SYSCLK_SRC_HXTAL
* @arg RCC_SYSCLK_SRC_PLLCLK
* @arg RCC_SYSCLK_SRC_RCL
* @arg RCC_SYSCLK_SRC_LXTAL
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_sysclk_source(uint32_t clocksource)
{
MODIFY_REG(RCC->CFG, RCC_CFG_SYSW, clocksource);
}
/**
* @brief <EFBFBD><EFBFBD>ȡϵͳʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>Ϣ
* @retval uint32_t ϵͳʱ<EFBFBD><EFBFBD>Դ
* @arg RCC_SYSCLK_SRC_STATUS_RCHSYS
* @arg RCC_SYSCLK_SRC_STATUS_HXTAL
* @arg RCC_SYSCLK_SRC_STATUS_PLLCLK
* @arg RCC_SYSCLK_SRC_STATUS_RCL
* @arg RCC_SYSCLK_SRC_STATUS_LXTAL
*/
__STATIC_INLINE uint32_t std_rcc_get_sysclk_source(void)
{
return(RCC->CFG & RCC_CFG_SYSWS);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>AHBʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param ahb_div AHB<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_HCLK_DIV1
* @arg RCC_HCLK_DIV2
* @arg ...
* @arg RCC_HCLK_DIV128
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_ahbdiv(uint32_t ahb_div)
{
MODIFY_REG(RCC->CFG, RCC_CFG_HPRE, ahb_div);
}
/**
* @brief <EFBFBD><EFBFBD>ȡAHBʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval uint32_t HCLKʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_HCLK_DIV1
* @arg RCC_HCLK_DIV2
* @arg ...
* @arg RCC_HCLK_DIV128
*/
__STATIC_INLINE uint32_t std_rcc_get_ahbdiv(void)
{
return(RCC->CFG & RCC_CFG_HPRE);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>APB1ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param apb1_div APB1<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_PCLK1_DIV1
* @arg RCC_PCLK1_DIV2
* @arg ...
* @arg RCC_PCLK1_DIV16
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_apb1div(uint32_t apb1_div)
{
MODIFY_REG(RCC->CFG, RCC_CFG_P1PRE, apb1_div);
}
/**
* @brief <EFBFBD><EFBFBD>ȡAPB1ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval uint32_t PCLK1ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_PCLK1_DIV1
* @arg RCC_PCLK1_DIV2
* @arg ...
* @arg RCC_PCLK1_DIV16
*/
__STATIC_INLINE uint32_t std_rcc_get_apb1div(void)
{
return(RCC->CFG & RCC_CFG_P1PRE);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>APB2ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param apb2_div APB1<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_PCLK2_DIV1
* @arg RCC_PCLK2_DIV2
* @arg ...
* @arg RCC_PCLK2_DIV16
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_apb2div(uint32_t apb2_div)
{
MODIFY_REG(RCC->CFG, RCC_CFG_P2PRE, apb2_div);
}
/**
* @brief <EFBFBD><EFBFBD>ȡAPB2ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval uint32_t PCLK2ʱ<EFBFBD>ӷ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_PCLK2_DIV1
* @arg RCC_PCLK2_DIV2
* @arg ...
* @arg RCC_PCLK2_DIV16
*/
__STATIC_INLINE uint32_t std_rcc_get_apb2div(void)
{
return(RCC->CFG & RCC_CFG_P2PRE);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>MCO<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
* @param mco_source MCO<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դѡ<EFBFBD><EFBFBD>
* @arg RCC_MCO_SRC_SYSCLK
* @arg RCC_MCO_SRC_RCH
* @arg RCC_MCO_SRC_HXTAL
* @arg RCC_MCO_SRC_PLLCLK
* @arg RCC_MCO_SRC_RCL
* @arg RCC_MCO_SRC_LXTAL
* @param mco_psc MCO<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_MCO_DIV1
* @arg RCC_MCO_DIV2
* @arg ...
* @arg RCC_MCO_DIV128
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_mco_config(uint32_t mco_source, uint32_t mco_psc)
{
MODIFY_REG(RCC->CFG, RCC_CFG_MCOSEL | RCC_CFG_MCOPRE, mco_source | mco_psc);
}
/**
* @brief <EFBFBD>ر<EFBFBD>HXTALʱ<EFBFBD><EFBFBD>
* @note <EFBFBD><EFBFBD><EFBFBD><EFBFBD>HXTALΪϵͳʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>䲻<EFBFBD>ܱ<EFBFBD>ֹͣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>û<EFBFBD>Ӧ<EFBFBD>Ƚ<EFBFBD>ϵͳʱ<EFBFBD><EFBFBD>Դ<EFBFBD>л<EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӣ<EFBFBD><EFBFBD>ٹرո<EFBFBD>ʱ<EFBFBD><EFBFBD>Դ
* @note <EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD>HXTALʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD>HXTALRDY<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_hxtal_disable(void)
{
RCC->CSR1 &= (~RCC_CSR1_HXTALON);
RCC->CSR1 &= (~RCC_CSR1_HXTALBYP);
}
/**
* @brief ʹ<EFBFBD><EFBFBD>HXTALʱ<EFBFBD><EFBFBD>
* @param mode HXTAL<EFBFBD><EFBFBD>ģʽѡ<EFBFBD><EFBFBD>
* @arg RCC_HXTAL_ON<EFBFBD><EFBFBD> ʹ<EFBFBD>ܾ<EFBFBD><EFBFBD><EFBFBD>ģʽ
* @arg RCC_HXTAL_BYPASS<EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD><EFBFBD>ⲿʱ<EFBFBD><EFBFBD>ģʽ
* @note ʹ<EFBFBD><EFBFBD>HXTAL<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD>ȴ<EFBFBD>HXTALRDY<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ø<EFBFBD>ʱ<EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_hxtal_enable(uint32_t mode)
{
if(mode == RCC_HXTAL_BYPASS)
{
RCC->CSR1 |= RCC_CSR1_HXTALBYP;
}
RCC->CSR1 |= RCC_CSR1_HXTALON;
}
/**
* @brief <EFBFBD><EFBFBD>ȡHXTAL ready<EFBFBD><EFBFBD>־
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>жϽ<EFBFBD><EFBFBD><EFBFBD>
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾHXTAL ready<EFBFBD><EFBFBD>λ
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾHXTAL readyδ<EFBFBD><EFBFBD>λ
*/
__STATIC_INLINE bool std_rcc_get_hxtal_ready(void)
{
return((RCC->CSR1 & RCC_CSR1_HXTALRDY) == RCC_CSR1_HXTALRDY);
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>HXTAL<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param drive_level HXTAL<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_HXTAL_DRIVE_LEVEL0
* @arg RCC_HXTAL_DRIVE_LEVEL1
* @arg RCC_HXTAL_DRIVE_LEVEL2
* @arg RCC_HXTAL_DRIVE_LEVEL3
* @retval <EFBFBD><EFBFBD>
*
*/
__STATIC_INLINE void std_rcc_hxtal_drive_config(uint32_t drive_level)
{
MODIFY_REG(RCC->CSR1, RCC_CSR1_HXTAL_DRV, (drive_level));
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>HXTALʱ<EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param drive_stabc HXTALʱ<EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_HXTAL_STAB_SEL_256
* @arg ...
* @arg RCC_HXTAL_STAB_SEL_16384
* @retval <EFBFBD><EFBFBD>
*
*/
__STATIC_INLINE void std_rcc_hxtal_stabc_config(uint32_t drive_stabc)
{
MODIFY_REG(RCC->STABC, RCC_STABC_HXTAL_STAB_SEL, (drive_stabc));
}
/**
* @brief <EFBFBD>ر<EFBFBD>LXTALʱ<EFBFBD><EFBFBD>
* @note <EFBFBD><EFBFBD><EFBFBD><EFBFBD>LXTALΪϵͳʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>䲻<EFBFBD>ܱ<EFBFBD>ֹͣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>û<EFBFBD>Ӧ<EFBFBD>Ƚ<EFBFBD>ϵͳʱ<EFBFBD><EFBFBD>Դ<EFBFBD>л<EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӣ<EFBFBD><EFBFBD>ٹرո<EFBFBD>ʱ<EFBFBD><EFBFBD>Դ
* @note <EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD>LXTALʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD>LXTALRDY<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @note <EFBFBD><EFBFBD><EFBFBD>øú<EFBFBD><EFBFBD><EFBFBD>ǰӦ<EFBFBD>ȵ<EFBFBD><EFBFBD><EFBFBD>std_pmu_vaon_write_enable(void)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCC_AWCR<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_lxtal_disable(void)
{
RCC->AWCR &= (~RCC_AWCR_LXTALON);
}
/**
* @brief ʹ<EFBFBD><EFBFBD>LXTALʱ<EFBFBD><EFBFBD>
* @param mode LXTAL<EFBFBD><EFBFBD><EFBFBD><EFBFBD>·ģʽѡ<EFBFBD><EFBFBD>
@arg RCC_LXTAL_ON
* @note ʹ<EFBFBD><EFBFBD>LXTAL<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD>ȴ<EFBFBD>LXTALRDY<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ø<EFBFBD>ʱ<EFBFBD><EFBFBD>
* @note <EFBFBD><EFBFBD><EFBFBD>øú<EFBFBD><EFBFBD><EFBFBD>ǰӦ<EFBFBD>ȵ<EFBFBD><EFBFBD><EFBFBD>std_pmu_vaon_write_enable(void)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCC_AWCR<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_lxtal_enable(uint32_t mode)
{
RCC->AWCR |= RCC_AWCR_LXTALON;
}
/**
* @brief <EFBFBD><EFBFBD>ȡLXTAL ready<EFBFBD><EFBFBD>־
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>жϽ<EFBFBD><EFBFBD><EFBFBD>
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾLXTAL ready<EFBFBD><EFBFBD>λ
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾLXTAL readyδ<EFBFBD><EFBFBD>λ
*/
__STATIC_INLINE bool std_rcc_get_lxtal_ready(void)
{
return((RCC->AWCR & RCC_AWCR_LXTALRDY) == RCC_AWCR_LXTALRDY);
}
/**
* @brief LXTALʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽѡ<EFBFBD><EFBFBD>
* @param lxtal_drv_mode LXTAL<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽѡ<EFBFBD><EFBFBD>
* @arg RCC_LXTAL_DRIVE_MODE_NORMAL<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ͨģʽ
* @arg RCC_LXTAL_DRIVE_MODE_ENHANCE<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǿģʽ
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_lxtal_drive_mode_config(uint32_t lxtal_drv_mode)
{
MODIFY_REG(RCC->AWCR, RCC_AWCR_LXTAL_DRV_MODE, (lxtal_drv_mode));
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>LXTALʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param drive_level LXTALʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_LXTAL_DRIVE_LEVEL0
* @arg RCC_LXTAL_DRIVE_LEVEL1
* @arg RCC_LXTAL_DRIVE_LEVEL2
* @arg RCC_LXTAL_DRIVE_LEVEL3
* @note <EFBFBD><EFBFBD><EFBFBD>øú<EFBFBD><EFBFBD><EFBFBD>ǰӦ<EFBFBD>ȵ<EFBFBD><EFBFBD><EFBFBD>std_pmu_vaon_write_enable(void)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCC_AWCR<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_lxtal_drive_config(uint32_t drive_level)
{
MODIFY_REG(RCC->AWCR, RCC_AWCR_LXTAL_DRV, (drive_level));
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>LXTALʱ<EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param drive_stabc LXTALʱ<EFBFBD><EFBFBD><EFBFBD>ȶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_LXTAL_STAB_SEL_256
* @arg ...
* @arg RCC_LXTAL_STAB_SEL_16384
* @note <EFBFBD><EFBFBD><EFBFBD>øú<EFBFBD><EFBFBD><EFBFBD>ǰӦ<EFBFBD>ȵ<EFBFBD><EFBFBD><EFBFBD>std_pmu_vaon_write_enable(void)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCC_AWCR<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_lxtal_stabc_config(uint32_t drive_stabc)
{
MODIFY_REG(RCC->AWCR, RCC_AWCR_LXTAL_STAB_SEL, (drive_stabc));
}
/**
* @brief ʹ<EFBFBD><EFBFBD>RCC<EFBFBD>ж<EFBFBD>
* @param interrupt ʹ<EFBFBD><EFBFBD>RCC<EFBFBD>ж<EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
* @arg RCC_INTERRUPT_RCL_READY
* @arg RCC_INTERRUPT_LXTAL_READY
* @arg RCC_INTERRUPT_RCH_READY
* @arg RCC_INTERRUPT_HXTAL_READY
* @arg RCC_INTERRUPT_PLL_READY
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_interrupt_enable(uint32_t interrupt)
{
RCC->IER |= (interrupt);
}
/**
* @brief <EFBFBD>ر<EFBFBD>RCC<EFBFBD>ж<EFBFBD>
* @param interrupt <EFBFBD>ر<EFBFBD>RCC<EFBFBD>ж<EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
* @arg RCC_INTERRUPT_RCL_READY
* @arg RCC_INTERRUPT_LXTAL_READY
* @arg RCC_INTERRUPT_RCH_READY
* @arg RCC_INTERRUPT_HXTAL_READY
* @arg RCC_INTERRUPT_PLL_READY
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_interrupt_disable(uint32_t interrupt)
{
RCC->IER &= (~(interrupt));
}
/**
* @brief <EFBFBD><EFBFBD>ȡRCC<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><EFBFBD>״̬
* @param interrupt RCC<EFBFBD>ж<EFBFBD>Դ<EFBFBD><EFBFBD>Ϣ
* @arg RCC_INTERRUPT_RCL_READY
* @arg RCC_INTERRUPT_LXTAL_READY
* @arg RCC_INTERRUPT_RCH_READY
* @arg RCC_INTERRUPT_HXTAL_READY
* @arg RCC_INTERRUPT_PLL_READY
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<EFBFBD>־<EFBFBD><EFBFBD>λ״̬
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʹ<EFBFBD><EFBFBD>
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>δʹ<EFBFBD><EFBFBD>
*/
__STATIC_INLINE bool std_rcc_get_interrupt_enable(uint32_t interrupt)
{
return((RCC->IER & (interrupt)) == (interrupt));
}
/**
* @brief <EFBFBD><EFBFBD>ȡRCC<EFBFBD>жϱ<EFBFBD>־״̬
* @param flag RCC<EFBFBD>жϱ<EFBFBD>־<EFBFBD><EFBFBD>Ϣ
* @arg RCC_FLAG_RCL_READY
* @arg RCC_FLAG_LXTAL_READY
* @arg RCC_FLAG_RCH_READY
* @arg RCC_FLAG_HXTAL_READY
* @arg RCC_FLAG_PLL_READY
* @arg RCC_FLAG_HXTALCSS
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<EFBFBD>־<EFBFBD><EFBFBD>λ״̬
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<EFBFBD>־<EFBFBD><EFBFBD>λ
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<EFBFBD>־δ<EFBFBD><EFBFBD>λ
*/
__STATIC_INLINE bool std_rcc_get_flag(uint32_t flag)
{
return((RCC->ISR & (flag)) == (flag));
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCC<EFBFBD><EFBFBD>־
* @param flags <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
* @arg RCC_CLEAR_RCL_READY
* @arg RCC_CLEAR_LXTAL_READY
* @arg RCC_CLEAR_RCH_READY
* @arg RCC_CLEAR_HXTAL_READY
* @arg RCC_CLEAR_PLL_READY
* @arg RCC_CLEAR_HXTALCSS
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_clear_flag(uint32_t flags)
{
RCC->ICR |= (flags);
}
/**
* @brief ʹ<EFBFBD><EFBFBD>RCLʱ<EFBFBD><EFBFBD>
* @note ʹ<EFBFBD><EFBFBD>RCL<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD>ȴ<EFBFBD>RCLRDY<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ø<EFBFBD>ʱ<EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_rcl_enable(void)
{
RCC->CSR2 |= RCC_CSR2_RCLON;
}
/**
* @brief <EFBFBD>ر<EFBFBD>RCLʱ<EFBFBD><EFBFBD>
* @note <EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCLΪϵͳʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>䲻<EFBFBD>ܱ<EFBFBD>ֹͣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>û<EFBFBD>Ӧ<EFBFBD>Ƚ<EFBFBD>ϵͳʱ<EFBFBD><EFBFBD>Դ<EFBFBD>л<EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӣ<EFBFBD><EFBFBD>ٹرո<EFBFBD>ʱ<EFBFBD><EFBFBD>Դ
* @note <EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD>RCLʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD>RCLRDY<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_rcl_disable(void)
{
RCC->CSR2 &= (~RCC_CSR2_RCLON);
}
/**
* @brief <EFBFBD><EFBFBD>ȡRCL ready<EFBFBD><EFBFBD>־
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>жϽ<EFBFBD><EFBFBD><EFBFBD>
* @arg true<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ʾRCL ready<EFBFBD><EFBFBD>λ
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾRCL readyδ<EFBFBD><EFBFBD>λ
*/
__STATIC_INLINE bool std_rcc_get_rcl_ready(void)
{
return((RCC->CSR2 & RCC_CSR2_RCLRDY) == RCC_CSR2_RCLRDY);
}
/**
* @brief ʹ<EFBFBD><EFBFBD>HXTAL CSS
* @note ʹ<EFBFBD><EFBFBD>HXTAL CSS<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>޷<EFBFBD><EFBFBD>رգ<EFBFBD>ֱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD>߷<EFBFBD><EFBFBD><EFBFBD>CSS<EFBFBD><EFBFBD><EFBFBD>ϲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_hxtal_css_enable(void)
{
RCC->CSR1 |= RCC_CSR1_HXTAL_CSSON;
}
/**
* @brief <EFBFBD><EFBFBD>ȡ<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>־
* @param reset_flag ָ<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD>ȡ<EFBFBD>ĸ<EFBFBD>λ<EFBFBD><EFBFBD>־
* @arg RCC_RESET_FLAG_LOCKUP
* @arg RCC_RESET_FLAG_OBL
* @arg RCC_RESET_FLAG_NRST
* @arg RCC_RESET_FLAG_PMU
* @arg RCC_RESET_FLAG_SW
* @arg RCC_RESET_FLAG_IWDG
* @arg RCC_RESET_FLAG_WWDG
* @arg RCC_RESET_FLAG_LPM
* @arg RCC_RESET_FLAG_ALL
* @retval bool <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>жϽ<EFBFBD><EFBFBD><EFBFBD>
* @arg true<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾָ<EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>λ<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD>λ
* @arg false<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾָ<EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>λ<EFBFBD><EFBFBD>־δ<EFBFBD><EFBFBD>λ
*/
__STATIC_INLINE bool std_rcc_get_reset_flag(uint32_t reset_flag)
{
return((RCC->CSR2 & (reset_flag)) == (reset_flag));
}
/**
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>־
* @note <EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>и<EFBFBD>λ<EFBFBD><EFBFBD>־
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_clear_reset_flags(void)
{
RCC->CSR2 |= RCC_CSR2_RMVF;
}
/**
* @brief GPIO<EFBFBD>˿<EFBFBD>ʱ<EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>
* @param gpiox_clock ָ<EFBFBD><EFBFBD>ʹ<EFBFBD>ܵ<EFBFBD>GPIOʱ<EFBFBD><EFBFBD>
* @arg RCC_PERIPH_CLK_GPIOA
* @arg ...
* @arg RCC_PERIPH_CLK_GPIOF
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_gpio_clk_enable(uint32_t gpiox_clock)
{
RCC->IOPEN |= gpiox_clock;
/* RCC<43><43>Χʱ<CEA7><CAB1><EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD><EFBFBD>ӳ<EFBFBD> */
__NOP(); __NOP(); __NOP();
}
/**
* @brief GPIO<EFBFBD>˿<EFBFBD>ʱ<EFBFBD>ӽ<EFBFBD>ֹ
* @param gpiox_clock ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD>GPIOʱ<EFBFBD><EFBFBD>
* @arg RCC_PERIPH_CLK_GPIOA
* @arg ...
* @arg RCC_PERIPH_CLK_GPIOF
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_gpio_clk_disable(uint32_t gpiox_clock)
{
RCC->IOPEN &= (~(gpiox_clock));
/* RCC<43><43>Χʱ<CEA7><CAB1><EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD><EFBFBD>ӳ<EFBFBD> */
__NOP(); __NOP(); __NOP();
}
/**
* @brief GPIO<EFBFBD>˿ڸ<EFBFBD>λ
* @param gpiox_rst ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>GPIO<EFBFBD>˿<EFBFBD>
* @arg RCC_PERIPH_RESET_GPIO_ALL
* @arg RCC_PERIPH_RESET_GPIOA
* @arg ...
* @arg RCC_PERIPH_RESET_GPIOF
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_gpio_reset(uint32_t gpiox_rst)
{
RCC->IOPRST |= (gpiox_rst);
RCC->IOPRST &= (~(gpiox_rst));
}
/**
* @brief AHB<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>
* @param periph_clock ָ<EFBFBD><EFBFBD>ʹ<EFBFBD>ܵ<EFBFBD>AHB<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
* @arg RCC_PERIPH_CLK_DMA
* @arg RCC_PERIPH_CLK_FLASH
* @arg RCC_PERIPH_CLK_CRC
* @arg RCC_PERIPH_CLK_AES
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_ahb_clk_enable(uint32_t periph_clock)
{
RCC->AHBEN |= periph_clock;
/* RCC<43><43>Χʱ<CEA7><CAB1><EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD><EFBFBD>ӳ<EFBFBD> */
__NOP(); __NOP(); __NOP();
}
/**
* @brief AHB<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӽ<EFBFBD>ֹ
* @param periph_clock ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD>AHB<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
* @arg RCC_PERIPH_CLK_DMA
* @arg RCC_PERIPH_CLK_FLASH
* @arg RCC_PERIPH_CLK_CRC
* @arg RCC_PERIPH_CLK_AES
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_ahb_clk_disable(uint32_t periph_clock)
{
RCC->AHBEN &= (~(periph_clock));
}
/**
* @brief AHB<EFBFBD><EFBFBD><EFBFBD>踴λ
* @param periph_rst ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>AHB<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_PERIPH_RESET_AHB
* @arg RCC_PERIPH_RESET_DMA
* @arg RCC_PERIPH_RESET_CRC
* @arg RCC_PERIPH_RESET_AES
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_ahb_reset(uint32_t periph_rst)
{
RCC->AHBRST |= (periph_rst);
RCC->AHBRST &= (~(periph_rst));
}
/**
* @brief APB1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>
* @param periph_clock ָ<EFBFBD><EFBFBD>ʹ<EFBFBD>ܵ<EFBFBD>APB1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
* @arg RCC_PERIPH_CLK_TIM3
* @arg RCC_PERIPH_CLK_TIM4
* @arg RCC_PERIPH_CLK_TIM5
* @arg RCC_PERIPH_CLK_TIM8
* @arg RCC_PERIPH_CLK_LCD
* @arg RCC_PERIPH_CLK_RTC
* @arg RCC_PERIPH_CLK_WWDG
* @arg RCC_PERIPH_CLK_SPI2
* @arg RCC_PERIPH_CLK_UART2
* @arg RCC_PERIPH_CLK_UART3
* @arg RCC_PERIPH_CLK_UART4
* @arg RCC_PERIPH_CLK_LPUART1
* @arg RCC_PERIPH_CLK_I2C1
* @arg RCC_PERIPH_CLK_LPUART2
* @arg RCC_PERIPH_CLK_PMU
* @arg RCC_PERIPH_CLK_LPTIM1
* @arg RCC_PERIPH_CLK_LPTIM2
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_apb1_clk_enable(uint32_t periph_clock)
{
RCC->APB1EN |= periph_clock;
/* RCC<43><43>Χʱ<CEA7><CAB1><EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD><EFBFBD>ӳ<EFBFBD> */
__NOP(); __NOP(); __NOP();
}
/**
* @brief APB1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӽ<EFBFBD>ֹ
* @param periph_clock ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD>APB1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
* @arg RCC_PERIPH_CLK_TIM3
* @arg RCC_PERIPH_CLK_TIM4
* @arg RCC_PERIPH_CLK_TIM5
* @arg RCC_PERIPH_CLK_TIM8
* @arg RCC_PERIPH_CLK_LCD
* @arg RCC_PERIPH_CLK_RTC
* @arg RCC_PERIPH_CLK_WWDG
* @arg RCC_PERIPH_CLK_SPI2
* @arg RCC_PERIPH_CLK_UART2
* @arg RCC_PERIPH_CLK_UART3
* @arg RCC_PERIPH_CLK_UART4
* @arg RCC_PERIPH_CLK_LPUART1
* @arg RCC_PERIPH_CLK_I2C1
* @arg RCC_PERIPH_CLK_LPUART2
* @arg RCC_PERIPH_CLK_PMU
* @arg RCC_PERIPH_CLK_LPTIM1
* @arg RCC_PERIPH_CLK_LPTIM2
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_apb1_clk_disable(uint32_t periph_clock)
{
RCC->APB1EN &= (~(periph_clock));
}
/**
* @brief APB1<EFBFBD><EFBFBD><EFBFBD>踴λ
* @param periph_rst ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>APB1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_PERIPH_RESET_APB1
* @arg RCC_PERIPH_RESET_TIM3
* @arg RCC_PERIPH_RESET_TIM4
* @arg RCC_PERIPH_RESET_TIM5
* @arg RCC_PERIPH_RESET_TIM8
* @arg RCC_PERIPH_RESET_LCD
* @arg RCC_PERIPH_RESET_SPI2
* @arg RCC_PERIPH_RESET_UART2
* @arg RCC_PERIPH_RESET_UART3
* @arg RCC_PERIPH_RESET_UART4
* @arg RCC_PERIPH_RESET_LPUART1
* @arg RCC_PERIPH_RESET_I2C1
* @arg RCC_PERIPH_RESET_LPUART2
* @arg RCC_PERIPH_RESET_LPTIM1
* @arg RCC_PERIPH_RESET_LPTIM2
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_apb1_reset(uint32_t periph_rst)
{
RCC->APB1RST |= (periph_rst);
RCC->APB1RST &= (~(periph_rst));
}
/**
* @brief APB2<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>
* @param periph_clock ָ<EFBFBD><EFBFBD>ʹ<EFBFBD>ܵ<EFBFBD>APB2<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
* @arg RCC_PERIPH_CLK_SYSCFG
* @arg RCC_PERIPH_CLK_TRNG
* @arg RCC_PERIPH_CLK_SPI1
* @arg RCC_PERIPH_CLK_USART1
* @arg RCC_PERIPH_CLK_ADC
* @arg RCC_PERIPH_CLK_DBG
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_apb2_clk_enable(uint32_t periph_clock)
{
RCC->APB2EN |= periph_clock;
/* RCC<43><43>Χʱ<CEA7><CAB1><EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD><EFBFBD>ӳ<EFBFBD> */
__NOP(); __NOP(); __NOP();
}
/**
* @brief APB2<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӽ<EFBFBD>ֹ
* @param periph_clock ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD>APB2<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
* @arg RCC_PERIPH_CLK_SYSCFG
* @arg RCC_PERIPH_CLK_TRNG
* @arg RCC_PERIPH_CLK_SPI1
* @arg RCC_PERIPH_CLK_USART1
* @arg RCC_PERIPH_CLK_ADC
* @arg RCC_PERIPH_CLK_DBG
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_apb2_clk_disable(uint32_t periph_clock)
{
RCC->APB2EN &= (~(periph_clock));
}
/**
* @brief APB2<EFBFBD><EFBFBD><EFBFBD>踴λ
* @param periph_rst ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>APB2<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @arg RCC_PERIPH_RESET_APB2
* @arg RCC_PERIPH_RESET_SYSCFG
* @arg RCC_PERIPH_RESET_TRNG
* @arg RCC_PERIPH_RESET_SPI1
* @arg RCC_PERIPH_RESET_USART1
* @arg RCC_PERIPH_RESET_ADC
* @arg RCC_PERIPH_RESET_DBG
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_apb2_reset(uint32_t periph_rst)
{
RCC->APB2RST |= (periph_rst);
RCC->APB2RST &= (~(periph_rst));
}
/**
* @brief ʹ<EFBFBD><EFBFBD>LOCKUP<EFBFBD><EFBFBD>λ
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_lockup_reset_enable(void)
{
RCC->CSR2 |= RCC_CSR2_LOCKUP_RSTEN;
}
/**
* @brief <EFBFBD><EFBFBD>ֹLOCKUP<EFBFBD><EFBFBD>λ
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_lockup_reset_disable(void)
{
RCC->CSR2 &= (~RCC_CSR2_LOCKUP_RSTEN);
}
/**
* @brief ADCʱ<EFBFBD><EFBFBD>Դѡ<EFBFBD><EFBFBD>
* @param adcclk_select ADCʱ<EFBFBD><EFBFBD>Դ
* @arg RCC_ADC_ASYNC_CLK_SRC_SYSCLK
* @arg RCC_ADC_ASYNC_CLK_SRC_SYS_DIV2
* @arg RCC_ADC_ASYNC_CLK_SRC_SYS_DIV4
* @arg RCC_ADC_ASYNC_CLK_SRC_RCH
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_adcclk_source(uint32_t adcclk_select)
{
MODIFY_REG(RCC->CLKSEL, RCC_CLKSEL_ADC_SEL, (adcclk_select));
}
/**
* @brief <EFBFBD><EFBFBD>ȡADCʱ<EFBFBD><EFBFBD>Դ
* @retval uint32_t <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>Ϣ
* @arg RCC_ADC_ASYNC_CLK_SRC_SYSCLK
* @arg RCC_ADC_ASYNC_CLK_SRC_SYS_DIV2
* @arg RCC_ADC_ASYNC_CLK_SRC_SYS_DIV4
* @arg RCC_ADC_ASYNC_CLK_SRC_RCH
*/
__STATIC_INLINE uint32_t std_rcc_get_adcclk_source(void)
{
return(RCC->CLKSEL & RCC_CLKSEL_ADC_SEL);
}
/**
* @brief LPTIM1ʱ<EFBFBD><EFBFBD>Դѡ<EFBFBD><EFBFBD>
* @param lptim1clk_select LPTIM1ʱ<EFBFBD><EFBFBD>Դ
* @arg RCC_LPTIM1_ASYNC_CLK_SRC_PCLK1
* @arg RCC_LPTIM1_ASYNC_CLK_SRC_RCL
* @arg RCC_LPTIM1_ASYNC_CLK_SRC_RCH
* @arg RCC_LPTIM1_ASYNC_CLK_SRC_LXTAL
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_lptim1clk_source(uint32_t lptim1clk_select)
{
MODIFY_REG(RCC->CLKSEL, RCC_CLKSEL_LPTIM1_SEL, (lptim1clk_select));
}
/**
* @brief <EFBFBD><EFBFBD>ȡLPTIM1ʱ<EFBFBD><EFBFBD>Դ
* @retval uint32_t <EFBFBD><EFBFBD><EFBFBD><EFBFBD>LPTIM1ʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>Ϣ
* @arg RCC_LPTIM1_ASYNC_CLK_SRC_PCLK1
* @arg RCC_LPTIM1_ASYNC_CLK_SRC_RCL
* @arg RCC_LPTIM1_ASYNC_CLK_SRC_RCH
* @arg RCC_LPTIM1_ASYNC_CLK_SRC_LXTAL
*/
__STATIC_INLINE uint32_t std_rcc_get_lptim1clk_source(void)
{
return(RCC->CLKSEL & RCC_CLKSEL_LPTIM1_SEL);
}
/**
* @brief LPTIM2ʱ<EFBFBD><EFBFBD>Դѡ<EFBFBD><EFBFBD>
* @param lptim2clk_select LPTIM2ʱ<EFBFBD><EFBFBD>Դ
* @arg RCC_LPTIM2_ASYNC_CLK_SRC_PCLK1
* @arg RCC_LPTIM2_ASYNC_CLK_SRC_RCL
* @arg RCC_LPTIM2_ASYNC_CLK_SRC_RCH
* @arg RCC_LPTIM2_ASYNC_CLK_SRC_LXTAL
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_lptim2clk_source(uint32_t lptim2clk_select)
{
MODIFY_REG(RCC->CLKSEL, RCC_CLKSEL_LPTIM2_SEL, (lptim2clk_select));
}
/**
* @brief <EFBFBD><EFBFBD>ȡLPTIM2ʱ<EFBFBD><EFBFBD>Դ
* @retval uint32_t <EFBFBD><EFBFBD><EFBFBD><EFBFBD>LPTIM2ʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>Ϣ
* @arg RCC_LPTIM2_ASYNC_CLK_SRC_PCLK1
* @arg RCC_LPTIM2_ASYNC_CLK_SRC_RCL
* @arg RCC_LPTIM2_ASYNC_CLK_SRC_RCH
* @arg RCC_LPTIM2_ASYNC_CLK_SRC_LXTAL
*/
__STATIC_INLINE uint32_t std_rcc_get_lptim2clk_source(void)
{
return(RCC->CLKSEL & RCC_CLKSEL_LPTIM2_SEL);
}
/**
* @brief I2C1ʱ<EFBFBD><EFBFBD>Դѡ<EFBFBD><EFBFBD>
* @param i2c1clk_select I2C1ʱ<EFBFBD><EFBFBD>Դ
* @arg RCC_I2C1_ASYNC_CLK_SRC_PCLK1
* @arg RCC_I2C1_ASYNC_CLK_SRC_SYSCLK
* @arg RCC_I2C1_ASYNC_CLK_SRC_RCH
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_i2c1clk_source(uint32_t i2c1clk_select)
{
MODIFY_REG(RCC->CLKSEL, RCC_CLKSEL_I2C1_SEL, (i2c1clk_select));
}
/**
* @brief <EFBFBD><EFBFBD>ȡI2C1ʱ<EFBFBD><EFBFBD>Դ
* @retval uint32_t <EFBFBD><EFBFBD><EFBFBD><EFBFBD>I2C1ʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>Ϣ
* @arg RCC_I2C1_ASYNC_CLK_SRC_PCLK1
* @arg RCC_I2C1_ASYNC_CLK_SRC_SYSCLK
* @arg RCC_I2C1_ASYNC_CLK_SRC_RCH
*/
__STATIC_INLINE uint32_t std_rcc_get_i2c1clk_source(void)
{
return(RCC->CLKSEL & RCC_CLKSEL_I2C1_SEL);
}
/**
* @brief LPUART1ʱ<EFBFBD><EFBFBD>Դѡ<EFBFBD><EFBFBD>
* @param lpuart1clk_select LPUART1ʱ<EFBFBD><EFBFBD>Դ
* @arg RCC_LPUART1_ASYNC_CLK_SRC_PCLK1
* @arg RCC_LPUART1_ASYNC_CLK_SRC_SYSCLK
* @arg RCC_LPUART1_ASYNC_CLK_SRC_RCH
* @arg RCC_LPUART1_ASYNC_CLK_SRC_LXTAL
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_lpuart1clk_source(uint32_t lpuart1clk_select)
{
MODIFY_REG(RCC->CLKSEL, RCC_CLKSEL_LPUART1_SEL, (lpuart1clk_select));
}
/**
* @brief <EFBFBD><EFBFBD>ȡLPUART1ʱ<EFBFBD><EFBFBD>Դ
* @retval uint32_t <EFBFBD><EFBFBD><EFBFBD><EFBFBD>LPUART1ʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>Ϣ
* @arg RCC_LPUART1_ASYNC_CLK_SRC_PCLK1
* @arg RCC_LPUART1_ASYNC_CLK_SRC_SYSCLK
* @arg RCC_LPUART1_ASYNC_CLK_SRC_RCH
* @arg RCC_LPUART1_ASYNC_CLK_SRC_LXTAL
*/
__STATIC_INLINE uint32_t std_rcc_get_lpuart1clk_source(void)
{
return(RCC->CLKSEL & RCC_CLKSEL_LPUART1_SEL);
}
/**
* @brief LPUART2ʱ<EFBFBD><EFBFBD>Դѡ<EFBFBD><EFBFBD>
* @param lpuart2clk_select LPUART2ʱ<EFBFBD><EFBFBD>Դ
* @arg RCC_LPUART2_ASYNC_CLK_SRC_PCLK1
* @arg RCC_LPUART2_ASYNC_CLK_SRC_SYSCLK
* @arg RCC_LPUART2_ASYNC_CLK_SRC_RCH
* @arg RCC_LPUART2_ASYNC_CLK_SRC_LXTAL
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_lpuart2clk_source(uint32_t lpuart2clk_select)
{
MODIFY_REG(RCC->CLKSEL, RCC_CLKSEL_LPUART2_SEL, (lpuart2clk_select));
}
/**
* @brief <EFBFBD><EFBFBD>ȡLPUART2ʱ<EFBFBD><EFBFBD>Դ
* @retval uint32_t <EFBFBD><EFBFBD><EFBFBD><EFBFBD>LPUART2ʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>Ϣ
* @arg RCC_LPUART2_ASYNC_CLK_SRC_PCLK1
* @arg RCC_LPUART2_ASYNC_CLK_SRC_SYSCLK
* @arg RCC_LPUART2_ASYNC_CLK_SRC_RCH
* @arg RCC_LPUART2_ASYNC_CLK_SRC_LXTAL
*/
__STATIC_INLINE uint32_t std_rcc_get_lpuart2clk_source(void)
{
return(RCC->CLKSEL & RCC_CLKSEL_LPUART2_SEL);
}
/**
* @brief RTC/LCDʱ<EFBFBD><EFBFBD>Դѡ<EFBFBD><EFBFBD>
* @param rtcclk_select RTC/LCDʱ<EFBFBD><EFBFBD>Դ
* @arg RCC_RTC_ASYNC_CLK_SRC_LXTAL
* @arg RCC_RTC_ASYNC_CLK_SRC_RCL
* @note <EFBFBD><EFBFBD><EFBFBD>øú<EFBFBD><EFBFBD><EFBFBD>ǰӦ<EFBFBD>ȵ<EFBFBD><EFBFBD><EFBFBD>std_pmu_vaon_write_enable(void)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCC_AWCR<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_set_rtcclk_source(uint32_t rtcclk_select)
{
MODIFY_REG(RCC->AWCR, RCC_AWCR_RTCSEL, (rtcclk_select));
}
/**
* @brief <EFBFBD><EFBFBD>ȡRTC/LCDʱ<EFBFBD><EFBFBD>Դ
* @retval uint32_t <EFBFBD><EFBFBD><EFBFBD><EFBFBD>RTC/LCDʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>Ϣ
* @arg RCC_RTC_ASYNC_CLK_SRC_LXTAL
* @arg RCC_RTC_ASYNC_CLK_SRC_RCL
*/
__STATIC_INLINE uint32_t std_rcc_get_rtcclk_source(void)
{
return(RCC->AWCR & RCC_AWCR_RTCSEL);
}
/**
* @brief ʹ<EFBFBD><EFBFBD>RTCʱ<EFBFBD><EFBFBD>
* @note <EFBFBD><EFBFBD><EFBFBD>øú<EFBFBD><EFBFBD><EFBFBD>ǰӦ<EFBFBD>ȵ<EFBFBD><EFBFBD><EFBFBD>std_pmu_vaon_write_enable(void)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCC_AWCR<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @note Ӧ<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>RTCʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD>ٵ<EFBFBD><EFBFBD>øú<EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>RTC KCLKʱ<EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_rtc_enable(void)
{
RCC->AWCR |= RCC_AWCR_RTCEN;
}
/**
* @brief <EFBFBD>ر<EFBFBD>RTCʱ<EFBFBD><EFBFBD>
* @note <EFBFBD><EFBFBD><EFBFBD>øú<EFBFBD><EFBFBD><EFBFBD>ǰӦ<EFBFBD>ȵ<EFBFBD><EFBFBD><EFBFBD>std_pmu_vaon_write_enable(void)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCC_AWCR<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_rtc_disable(void)
{
RCC->AWCR &= (~RCC_AWCR_RTCEN);
}
/**
* @brief ʹ<EFBFBD><EFBFBD>RCH<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @note ʹ<EFBFBD>ܺ<EFBFBD><EFBFBD><EFBFBD>Stopģʽ<EFBFBD>£<EFBFBD>RCH<EFBFBD>Ծɱ<EFBFBD><EFBFBD>ִ<EFBFBD><EFBFBD><EFBFBD>״̬<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>LPUART<EFBFBD>Ĺ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCH<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨѶ<EFBFBD>ٶ<EFBFBD>
* @note <EFBFBD>˹<EFBFBD><EFBFBD>ܵ<EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCHONλ<EFBFBD><EFBFBD>Ӱ<EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_rchawon_enable(void)
{
RCC->CSR1 |= RCC_CSR1_RCH_AWON;
}
/**
* @brief <EFBFBD><EFBFBD>ֹRCH<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @note <EFBFBD>˹<EFBFBD><EFBFBD>ܵ<EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCHONλ<EFBFBD><EFBFBD>Ӱ<EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_rchawon_disable(void)
{
RCC->CSR1 &= (~RCC_CSR1_RCH_AWON);
}
/**
* @brief VCORE_AON <EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
* @note <EFBFBD>˺<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RTC/TAMP<EFBFBD><EFBFBD><EFBFBD>裨<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݼĴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> RCC_AWCR<EFBFBD><EFBFBD><EFBFBD>ֿ<EFBFBD><EFBFBD><EFBFBD>λ
* @note <EFBFBD><EFBFBD><EFBFBD>øú<EFBFBD><EFBFBD><EFBFBD>ǰӦ<EFBFBD>ȵ<EFBFBD><EFBFBD><EFBFBD>std_pmu_vaon_write_enable(void)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RCC_AWCR<EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_vcore_aon_reset(void)
{
RCC->AWCR |= RCC_AWCR_AW_RST;
RCC->AWCR &= (~RCC_AWCR_AW_RST);
}
/**
* @brief дRCLУ׼ֵ
* @param cal_value RCLУ׼ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΧΪ<EFBFBD><EFBFBD>0x00~0x1F
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_write_rcl_calibration(uint32_t cal_value)
{
MODIFY_REG(RCC->RCLCAL, RCC_RCLCAL_RCL_CAL, cal_value << RCC_RCLCAL_RCL_CAL_POS);
}
/**
* @brief <EFBFBD><EFBFBD>ȡRCLУ׼ֵ
* @retval uint32_t RCLУ׼ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΧΪ<EFBFBD><EFBFBD>0x00~0x1F
*/
__STATIC_INLINE uint32_t std_rcc_read_rcl_calibration(void)
{
return(RCC->RCLCAL & RCC_RCLCAL_RCL_CAL);
}
/**
* @brief дRCHУ׼ֵ
* @param cal_value RCHУ׼ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΧΪ<EFBFBD><EFBFBD>0x00~0x7F
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_write_rch_calibration(uint32_t cal_value)
{
MODIFY_REG(RCC->RCHCAL, RCC_RCHCAL_RCH_CAL, cal_value << RCC_RCHCAL_RCH_CAL_POS);
}
/**
* @brief <EFBFBD><EFBFBD>ȡRCHУ׼ֵ
* @retval uint32_t RCHУ׼ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΧΪ<EFBFBD><EFBFBD>0x00~0x7F
*/
__STATIC_INLINE uint32_t std_rcc_read_rch_calibration(void)
{
return(RCC->RCHCAL & RCC_RCHCAL_RCH_CAL);
}
/**
* @brief дVREFBUF<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹУ׼ֵ
* @param cal_value VREFBUFУ׼ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΧΪ<EFBFBD><EFBFBD>0x00~0x7F
* @retval <EFBFBD><EFBFBD>
*/
__STATIC_INLINE void std_rcc_write_vrefbuf_calibration(uint32_t cal_value)
{
MODIFY_REG(RCC->VREFBUFCAL, RCC_VRBUFCAL_VRBUF_CAL, cal_value);
}
/**
* @brief <EFBFBD><EFBFBD>ȡVREFBUF<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹУ׼ֵ
* @retval uint32_t VREFBUFУ׼ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΧΪ<EFBFBD><EFBFBD>0x00~0x7F
*/
__STATIC_INLINE uint32_t std_rcc_read_vrefbuf_calibration(void)
{
return(RCC->VREFBUFCAL & RCC_VRBUFCAL_VRBUF_CAL);
}
/* <20><>ȡʱ<C8A1><CAB1>Ƶ<EFBFBD>ʺ<EFBFBD><CABA><EFBFBD> */
uint32_t std_rcc_get_sysclkfreq(void);
uint32_t std_rcc_get_pllfreq(void);
uint32_t std_rcc_get_hclkfreq(void);
uint32_t std_rcc_get_pclk1freq(void);
uint32_t std_rcc_get_pclk2freq(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* CIU32L051_STD_RCC_H */