198 lines
5.3 KiB
C
198 lines
5.3 KiB
C
/************************************************************************************************/
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/**
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* @file system_ciu32l051.c
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* @author MCU Ecosystem Development Team
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* @brief CMSIS Device System Source File for CIU32L051.
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*
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*
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**************************************************************************************************
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* @attention
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* Copyright (c) CEC Huada Electronic Design Co.,Ltd. All rights reserved.
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*
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**************************************************************************************************
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*/
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/************************************************************************************************/
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/**
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* @addtogroup CMSIS
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* @{
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*
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* @addtogroup Device_System Device System
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* @{
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*
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*/
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/************************************************************************************************/
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/*------------------------------------------includes--------------------------------------------*/
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#include "ciu32l051.h"
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#include "rtthread.h"
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/*--------------------------------------------define--------------------------------------------*/
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/************************************************************************************************/
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/**
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* @defgroup Device_System_Constants Device System Constants
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* @{
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*/
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/************************************************************************************************/
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#if !defined (HXTAL_VALUE)
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#define HXTAL_VALUE (8000000UL) /**< HXTAL clock frequency(Hz) */
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#endif
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#if !defined (LXTAL_VALUE)
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#define LXTAL_VALUE (32768UL) /**< LXTAL clock frequency(Hz) */
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#endif
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#if !defined (RCH_VALUE)
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#define RCH_VALUE (16000000UL) /**< RCH clock frequency(Hz) */
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#endif
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#if !defined (RCL_VALUE)
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#define RCL_VALUE (32000UL) /**< RCL clock frequency(Hz) */
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#endif
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/**
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* @}
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*/
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/*--------------------------------------------variables-----------------------------------------*/
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/* The SystemCoreClock variable is the system core clock(HCLK) frequency.*/
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uint32_t SystemCoreClock = RCH_VALUE;
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const uint32_t g_ahb_divider_table[8] = {1UL, 2UL, 4UL, 8UL, 16UL, 32UL, 64UL, 128UL};
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const uint32_t g_apb_divider_table[8] = {1UL, 1UL, 1UL, 1UL, 2UL, 4UL, 8UL, 16UL};
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#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
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extern uint32_t __vector_table;
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#endif
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/*-------------------------------------------functions------------------------------------------*/
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/************************************************************************************************/
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/**
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* @addtogroup Device_System_External_Functions
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* @{
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*
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*/
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/************************************************************************************************/
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/**
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* @brief MCU system initialization function
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Configure the vector table location add offset address */
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#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
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SCB->VTOR = (uint32_t) &__vector_table;
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#endif
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SystemCoreClock = RCH_VALUE;
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}
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/**
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* @brief System core clock(HCLK) update function
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*
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* @note This function is used to update the variable SystemCoreClock
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* and must be called whenever HCLK is changed
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp,tmp_clock;
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uint32_t pllsource;
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uint32_t pllm,plln,plldiv;
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uint32_t rchdiv;
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/* Get SYSCLK source */
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switch (RCC->CFG & RCC_CFG_SYSWS_MASK)
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{
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case RCC_CFG_SYSWS_HXTAL: /* HXTAL used as system clock */
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{
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tmp_clock = HXTAL_VALUE;
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}break;
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case RCC_CFG_SYSWS_LXTAL: /* LXTAL used as system clock */
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{
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tmp_clock = LXTAL_VALUE;
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}break;
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case RCC_CFG_SYSWS_RCL: /* RCL used as system clock */
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{
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tmp_clock = RCL_VALUE;
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}break;
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case RCC_CFG_SYSWS_PLL: /* PLL used as system clock */
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{
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pllsource = (RCC->PLLCFG & RCC_PLLCFG_PLLSRC_MASK);
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if(RCC_PLLCFG_PLLSRC_HXTAL == pllsource)
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{
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tmp = HXTAL_VALUE;
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}
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else if(RCC_PLLCFG_PLLSRC_RCH == pllsource)
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{
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tmp = RCH_VALUE;
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}
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else
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{
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tmp = 0;
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}
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pllm = (RCC->PLLCFG & RCC_PLLCFG_PLLM_MASK)>>RCC_PLLCFG_PLLM_POS;
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plln = (RCC->PLLCFG & RCC_PLLCFG_PLLN_MASK)>>RCC_PLLCFG_PLLN_POS;
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if(pllm == 0)
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{
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pllm = 32;
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}
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if(plln == 0)
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{
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plln = 8;
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}
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tmp = tmp*pllm/plln;
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plldiv = (RCC->PLLCFG & RCC_PLLCFG_PLLDIV_MASK)>>RCC_PLLCFG_PLLDIV_POS;
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tmp_clock = tmp/(1UL<<plldiv);
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}break;
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case RCC_CFG_SYSWS_RCHSYS: /* RCH used as system clock */
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default: /* RCH used as system clock */
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{
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rchdiv = (1UL << ((RCC->CSR1 & (RCC_CSR1_RCHDIV_MASK))>> RCC_CSR1_RCHDIV_POS));
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tmp_clock = (RCH_VALUE/rchdiv);
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}break;
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}
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/* Compute HCLK clock frequency */
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tmp = g_ahb_divider_table[((RCC->CFG & RCC_CFG_HPRE_MASK) >> RCC_CFG_HPRE_POS)];
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SystemCoreClock = tmp_clock/tmp;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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