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IoT_SCV_CH584M
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IoT_SCV_CH584M/bsp/src/bsp_uart.c

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bmp390中断
2024-12-11 16:21:57 +08:00
#include "bsp_uart.h"
#include "bsp_ml307r.h"
#include "lwrb.h"
#include "CH58x_uart.h"
#include "shell_port.h"
#define UART1_RX_BUFFER_LENGTH 512U
#define UART1_TX_BUFFER_LENGTH 512U
#define UART3_RX_BUFFER_LENGTH 1024U
#define UART3_TX_BUFFER_LENGTH 1024U
lwrb_t uart1_rx_t;
lwrb_t uart1_tx_t;
uint8_t uart1_tx_buf[UART1_TX_BUFFER_LENGTH] = {0};
uint8_t uart1_rx_buf[UART1_RX_BUFFER_LENGTH] = {0};
lwrb_t uart3_rx_t;
lwrb_t uart3_tx_t;
uint8_t uart3_tx_buf[UART3_TX_BUFFER_LENGTH] = {0};
uint8_t uart3_rx_buf[UART3_RX_BUFFER_LENGTH] = {0};
//<2F><><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD>
unsigned int BSP_Uart1_Receive_Data(void *buf, unsigned int len)
{
return lwrb_read(&uart1_rx_t, buf, len);
}
//<2F><><EFBFBD>ڷ<EFBFBD><DAB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
unsigned int BSP_Uart1_Send_Data(const void *buf, unsigned int len)
{
unsigned int ret;
ret = lwrb_write(&uart1_tx_t, buf, len);
UART1_INTCfg(ENABLE, RB_IER_THR_EMPTY);
return ret;
}
//<2F><><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD>
unsigned int BSP_Uart3_Receive_Data(void *buf, unsigned int len)
{
return lwrb_write(&uart3_rx_t, buf, len);
}
//<2F><><EFBFBD>ڷ<EFBFBD><DAB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
unsigned int BSP_Uart3_Send_Data(const void *buf, unsigned int len)
{
unsigned int ret;
ret = lwrb_write(&uart3_tx_t, buf, len);
UART3_INTCfg(ENABLE, RB_IER_THR_EMPTY);
return ret;
}
/**
* \brief Buffer event function
*/
static void Uart1_evt_fn(struct lwrb* buff, lwrb_evt_type_t evt, lwrb_sz_t bp)
{
switch (evt)
{
case LWRB_EVT_RESET:
printf("[EVT] Buffer reset event!\r\n");
break;
case LWRB_EVT_READ:
printf("[EVT] Buffer read event: %d byte(s)!\r\n", (int)bp);
break;
case LWRB_EVT_WRITE:
printf("[EVT] Buffer write event: %d byte(s)!\r\n", (int)bp);
break;
default: break;
}
}
void UART1_FifoInit(void)
{
lwrb_init(&uart1_tx_t, uart1_tx_buf, sizeof(uart1_tx_buf));
lwrb_init(&uart1_rx_t, uart1_rx_buf, sizeof(uart1_rx_buf));
// lwrb_set_evt_fn(&uart1_rx_t, Uart1_evt_fn);
}
void UART3_FifoInit(void)
{
lwrb_init(&uart3_tx_t, uart3_tx_buf, sizeof(uart3_tx_buf));
lwrb_init(&uart3_rx_t, uart3_rx_buf, sizeof(uart3_rx_buf));
lwrb_set_evt_fn(&uart1_rx_t, Uart1_evt_fn);
}
void BSP_UART1_Init(void)
{
GPIOPinRemap(ENABLE, RB_PIN_UART1);
/* <20><><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO<49><4F>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ô<EFBFBD><C3B4><EFBFBD> */
GPIOB_SetBits(ML307_UART_RX_PIN);
GPIOB_ModeCfg(ML307_UART_RX_PIN, GPIO_ModeIN_PU); // RXD-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
GPIOB_ModeCfg(ML307_UART_TX_PIN, GPIO_ModeOut_PP_5mA); // TXD-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO<49><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD>ƽ
UART1_DefInit();
UART1_BaudRateCfg(115200);
UART1_ByteTrigCfg(UART_1BYTE_TRIG);
// <20>жϷ<D0B6>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
UART1_INTCfg(ENABLE, RB_IER_LINE_STAT | RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
PFIC_EnableIRQ(UART1_IRQn);
UART1_FifoInit();
}
void BSP_UART3_Init(void)
{
GPIOPinRemap(ENABLE, RB_PIN_UART3);
/* <20><><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>3<EFBFBD><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO<49><4F>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ô<EFBFBD><C3B4><EFBFBD> */
GPIOB_SetBits(UART3_TX_PIN);
GPIOB_ModeCfg(UART3_RX_PIN, GPIO_ModeIN_PU); // RXD-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
GPIOB_ModeCfg(UART3_TX_PIN, GPIO_ModeOut_PP_5mA); // TXD-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO<49><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD>ƽ
UART3_DefInit();
UART3_BaudRateCfg(460800);
UART3_ByteTrigCfg(UART_1BYTE_TRIG);
// <20>жϷ<D0B6>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
UART3_INTCfg(ENABLE, RB_IER_LINE_STAT | RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
PFIC_EnableIRQ(UART3_IRQn);
UART3_FifoInit();
userShellInit();
}
/*********************************************************************
* @fn UART1_IRQHandler
*
* @brief UART1<EFBFBD>жϺ<EFBFBD><EFBFBD><EFBFBD>
*
* @return none
*/
__INTERRUPT
__HIGH_CODE
void UART1_IRQHandler(void)
{
uint8_t data;
switch(UART1_GetITFlag())
{
case UART_II_LINE_STAT: // <20><>·״̬<D7B4><CCAC><EFBFBD><EFBFBD>
{
// UART1_GetLinSTA();
break;
}
case UART_II_RECV_RDY:
data = UART1_RecvByte();
lwrb_write(&uart1_rx_t, &data, 1);
break;
case UART_II_RECV_TOUT: // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
break;
case UART_II_THR_EMPTY: // <20><><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>գ<EFBFBD><D5A3>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
if(lwrb_read(&uart1_tx_t, &data, 1))
{
UART1_SendByte(data);
}
else
{
UART1_INTCfg(DISABLE, RB_IER_THR_EMPTY);
}
break;
case UART_II_MODEM_CHG: // ֻ֧<D6BB>ִ<EFBFBD><D6B4><EFBFBD>0
break;
default:
break;
}
}
/*********************************************************************
* @fn UART3_IRQHandler
*
* @brief UART1<EFBFBD>жϺ<EFBFBD><EFBFBD><EFBFBD>
*
* @return none
*/
__INTERRUPT
__HIGH_CODE
void UART3_IRQHandler(void)
{
uint8_t data;
switch(UART3_GetITFlag())
{
case UART_II_LINE_STAT: // <20><>·״̬<D7B4><CCAC><EFBFBD><EFBFBD>
{
// UART1_GetLinSTA();
break;
}
case UART_II_RECV_RDY:
case UART_II_RECV_TOUT: //<2F><><EFBFBD>ճ<EFBFBD>ʱ
while(R8_UART3_RFC)
{
shellHandler(&shell, R8_UART3_RBR);
}
break;
case UART_II_THR_EMPTY: // <20><><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>գ<EFBFBD><D5A3>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
if(lwrb_get_full(&uart3_tx_t))
{
lwrb_read(&uart3_tx_t, &data, 1);
UART3_SendByte(data);
}
else
{
UART3_INTCfg(DISABLE, RB_IER_THR_EMPTY);
}
break;
case UART_II_MODEM_CHG: // ֻ֧<D6BB>ִ<EFBFBD><D6B4><EFBFBD>0
break;
default:
break;
}
}