2024-12-11 16:21:57 +08:00
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#include "bsp_uart.h"
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#include "bsp_ml307r.h"
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#include "lwrb.h"
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#include "CH58x_uart.h"
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#include "shell_port.h"
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2025-04-07 14:59:43 +08:00
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#include "SLEEP.h"
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#include "CONFIG.h"
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#include "log.h"
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2024-12-11 16:21:57 +08:00
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#define UART1_RX_BUFFER_LENGTH 512U
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#define UART1_TX_BUFFER_LENGTH 512U
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#define UART3_RX_BUFFER_LENGTH 1024U
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#define UART3_TX_BUFFER_LENGTH 1024U
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2025-04-07 14:59:43 +08:00
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void BSP_Shell_SetActive(void);
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2024-12-11 16:21:57 +08:00
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lwrb_t uart1_rx_t;
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lwrb_t uart1_tx_t;
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uint8_t uart1_tx_buf[UART1_TX_BUFFER_LENGTH] = {0};
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uint8_t uart1_rx_buf[UART1_RX_BUFFER_LENGTH] = {0};
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lwrb_t uart3_rx_t;
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lwrb_t uart3_tx_t;
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uint8_t uart3_tx_buf[UART3_TX_BUFFER_LENGTH] = {0};
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uint8_t uart3_rx_buf[UART3_RX_BUFFER_LENGTH] = {0};
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//<2F><><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD>
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unsigned int BSP_Uart1_Receive_Data(void *buf, unsigned int len)
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{
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return lwrb_read(&uart1_rx_t, buf, len);
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}
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//<2F><><EFBFBD>ڷ<EFBFBD><DAB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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unsigned int BSP_Uart1_Send_Data(const void *buf, unsigned int len)
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{
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unsigned int ret;
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ret = lwrb_write(&uart1_tx_t, buf, len);
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UART1_INTCfg(ENABLE, RB_IER_THR_EMPTY);
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return ret;
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}
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//<2F><><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD>
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unsigned int BSP_Uart3_Receive_Data(void *buf, unsigned int len)
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{
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2025-03-31 17:33:05 +08:00
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// return lwrb_write(&uart3_rx_t, buf, len);
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return lwrb_read(&uart3_rx_t, buf, len);
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2024-12-11 16:21:57 +08:00
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}
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//<2F><><EFBFBD>ڷ<EFBFBD><DAB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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unsigned int BSP_Uart3_Send_Data(const void *buf, unsigned int len)
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{
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unsigned int ret;
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ret = lwrb_write(&uart3_tx_t, buf, len);
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UART3_INTCfg(ENABLE, RB_IER_THR_EMPTY);
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return ret;
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}
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/**
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* \brief Buffer event function
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*/
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static void Uart1_evt_fn(struct lwrb* buff, lwrb_evt_type_t evt, lwrb_sz_t bp)
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{
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switch (evt)
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{
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case LWRB_EVT_RESET:
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printf("[EVT] Buffer reset event!\r\n");
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break;
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case LWRB_EVT_READ:
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printf("[EVT] Buffer read event: %d byte(s)!\r\n", (int)bp);
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break;
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case LWRB_EVT_WRITE:
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printf("[EVT] Buffer write event: %d byte(s)!\r\n", (int)bp);
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break;
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default: break;
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}
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}
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void UART1_FifoInit(void)
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{
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lwrb_init(&uart1_tx_t, uart1_tx_buf, sizeof(uart1_tx_buf));
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lwrb_init(&uart1_rx_t, uart1_rx_buf, sizeof(uart1_rx_buf));
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// lwrb_set_evt_fn(&uart1_rx_t, Uart1_evt_fn);
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}
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void UART3_FifoInit(void)
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{
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lwrb_init(&uart3_tx_t, uart3_tx_buf, sizeof(uart3_tx_buf));
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lwrb_init(&uart3_rx_t, uart3_rx_buf, sizeof(uart3_rx_buf));
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2025-03-20 11:26:08 +08:00
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//lwrb_set_evt_fn(&uart1_rx_t, Uart1_evt_fn);
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2024-12-11 16:21:57 +08:00
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}
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void BSP_UART1_Init(void)
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{
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GPIOPinRemap(ENABLE, RB_PIN_UART1);
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/* <20><><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO<49><4F>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ô<EFBFBD><C3B4><EFBFBD> */
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2025-03-20 11:26:08 +08:00
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GPIOB_SetBits(ML307_UART_TX_PIN);
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2024-12-11 16:21:57 +08:00
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GPIOB_ModeCfg(ML307_UART_RX_PIN, GPIO_ModeIN_PU); // RXD-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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GPIOB_ModeCfg(ML307_UART_TX_PIN, GPIO_ModeOut_PP_5mA); // TXD-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO<49><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD>ƽ
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UART1_DefInit();
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UART1_BaudRateCfg(115200);
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UART1_ByteTrigCfg(UART_1BYTE_TRIG);
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// <20>жϷ<D0B6>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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UART1_INTCfg(ENABLE, RB_IER_LINE_STAT | RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
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PFIC_EnableIRQ(UART1_IRQn);
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UART1_FifoInit();
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}
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void BSP_UART3_Init(void)
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{
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GPIOPinRemap(ENABLE, RB_PIN_UART3);
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/* <20><><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>3<EFBFBD><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO<49><4F>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ô<EFBFBD><C3B4><EFBFBD> */
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GPIOB_SetBits(UART3_TX_PIN);
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GPIOB_ModeCfg(UART3_RX_PIN, GPIO_ModeIN_PU); // RXD-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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GPIOB_ModeCfg(UART3_TX_PIN, GPIO_ModeOut_PP_5mA); // TXD-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO<49><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD>ƽ
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UART3_DefInit();
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2025-04-07 14:59:43 +08:00
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UART3_BaudRateCfg(115200); //460800
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2024-12-11 16:21:57 +08:00
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UART3_ByteTrigCfg(UART_1BYTE_TRIG);
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2025-04-07 14:59:43 +08:00
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2024-12-11 16:21:57 +08:00
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// <20>жϷ<D0B6>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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UART3_INTCfg(ENABLE, RB_IER_LINE_STAT | RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
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PFIC_EnableIRQ(UART3_IRQn);
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UART3_FifoInit();
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userShellInit();
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}
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2025-04-07 14:59:43 +08:00
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static tmosTaskID shell_timeout_task_id = INVALID_TASK_ID;
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#define SHELL_TIMEOUT_EVT 0x0001
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/**
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* @brief <EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>ϵͳ˯<EFBFBD><EFBFBD>
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*/
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static uint16_t BSP_Shell_TimeoutTask(uint8_t task_id, uint16_t events)
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{
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if (events & SHELL_TIMEOUT_EVT)
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{
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printf("Shell_Timeout UART3 enter low power mode\r\n");
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BSP_RequestSleep();
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return (events ^ SHELL_TIMEOUT_EVT);
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}
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return 0;
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}
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/**
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* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>Shell<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
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*/
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void BSP_Shell_StartTimeoutTimer(void)
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{
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if (shell_timeout_task_id == INVALID_TASK_ID)
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{
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shell_timeout_task_id = TMOS_ProcessEventRegister(BSP_Shell_TimeoutTask);
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}
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tmos_stop_task(shell_timeout_task_id, SHELL_TIMEOUT_EVT);
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tmos_start_task(shell_timeout_task_id, SHELL_TIMEOUT_EVT, MS1_TO_SYSTEM_TIME(SHELL_ACTIVITY_TIMEOUT));
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}
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/**
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* @brief <EFBFBD><EFBFBD>Shell<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>״̬<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹϵͳ˯<EFBFBD><EFBFBD>
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*/
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void BSP_Shell_SetActive(void)
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{
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BSP_BlockSleep();
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BSP_Shell_StartTimeoutTimer();
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}
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2024-12-11 16:21:57 +08:00
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/*********************************************************************
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* @fn UART1_IRQHandler
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*
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* @brief UART1<EFBFBD>жϺ<EFBFBD><EFBFBD><EFBFBD>
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*
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* @return none
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*/
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__INTERRUPT
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__HIGH_CODE
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void UART1_IRQHandler(void)
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{
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2025-03-20 11:26:08 +08:00
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uint8_t data,q;
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// q = UART1_GetITFlag();
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// printf("q1 = %#x\r\n", q);
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2024-12-11 16:21:57 +08:00
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switch(UART1_GetITFlag())
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{
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case UART_II_LINE_STAT: // <20><>·״̬<D7B4><CCAC><EFBFBD><EFBFBD>
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{
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// UART1_GetLinSTA();
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break;
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}
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case UART_II_RECV_RDY:
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data = UART1_RecvByte();
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2025-03-20 11:26:08 +08:00
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UART3_SendByte(data);
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2024-12-11 16:21:57 +08:00
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lwrb_write(&uart1_rx_t, &data, 1);
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2025-03-20 11:26:08 +08:00
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2024-12-11 16:21:57 +08:00
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break;
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case UART_II_RECV_TOUT: // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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break;
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case UART_II_THR_EMPTY: // <20><><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>գ<EFBFBD><D5A3>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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if(lwrb_read(&uart1_tx_t, &data, 1))
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{
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UART1_SendByte(data);
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}
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else
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{
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UART1_INTCfg(DISABLE, RB_IER_THR_EMPTY);
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}
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break;
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case UART_II_MODEM_CHG: // ֻ֧<D6BB>ִ<EFBFBD><D6B4><EFBFBD>0
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break;
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default:
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break;
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}
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}
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/*********************************************************************
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* @fn UART3_IRQHandler
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*
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* @brief UART1<EFBFBD>жϺ<EFBFBD><EFBFBD><EFBFBD>
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*
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* @return none
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*/
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__INTERRUPT
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__HIGH_CODE
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void UART3_IRQHandler(void)
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{
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2025-03-20 11:26:08 +08:00
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uint8_t data,q;
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// q = UART3_GetITFlag();
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// printf("q3 = %#x\r\n", q);
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2024-12-11 16:21:57 +08:00
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switch(UART3_GetITFlag())
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{
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case UART_II_LINE_STAT: // <20><>·״̬<D7B4><CCAC><EFBFBD><EFBFBD>
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{
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// UART1_GetLinSTA();
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break;
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}
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case UART_II_RECV_RDY:
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case UART_II_RECV_TOUT: //<2F><><EFBFBD>ճ<EFBFBD>ʱ
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2025-04-07 14:59:43 +08:00
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BSP_Shell_SetActive();
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2024-12-11 16:21:57 +08:00
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while(R8_UART3_RFC)
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{
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2025-04-07 14:59:43 +08:00
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logDebug("shellHandler \r\n");
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2024-12-11 16:21:57 +08:00
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shellHandler(&shell, R8_UART3_RBR);
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}
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break;
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case UART_II_THR_EMPTY: // <20><><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>գ<EFBFBD><D5A3>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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if(lwrb_get_full(&uart3_tx_t))
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{
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lwrb_read(&uart3_tx_t, &data, 1);
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UART3_SendByte(data);
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}
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else
|
|
|
|
|
{
|
|
|
|
|
UART3_INTCfg(DISABLE, RB_IER_THR_EMPTY);
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|
|
|
|
}
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|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case UART_II_MODEM_CHG: // ֻ֧<D6BB>ִ<EFBFBD><D6B4><EFBFBD>0
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
2025-04-07 14:59:43 +08:00
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