55 lines
1.2 KiB
C
55 lines
1.2 KiB
C
|
/***
|
||
|
|
* @Author: mbw
|
||
|
|
* @Date: 2024-10-09 08:42:14
|
||
|
|
* @LastEditors: mbw && 1600520629@qq.com
|
||
|
|
* @LastEditTime: 2024-10-17 09:14:26
|
||
|
|
* @FilePath: \JT-DT-YD4N02A_RTT_MRS-4G\libcpu\cpu\cpuport.h
|
||
|
|
* @Description:
|
||
|
|
* @
|
||
|
|
* @Copyright (c) 2024 by ${git_name_email}, All Rights Reserved.
|
||
|
|
*/
|
||
|
|
/*
|
||
|
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||
|
|
*
|
||
|
|
* SPDX-License-Identifier: Apache-2.0
|
||
|
|
*
|
||
|
|
* Change Logs:
|
||
|
|
* Date Author Notes
|
||
|
|
* 2021-09-09 WCH the first version
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifndef CPUPORT_H__
|
||
|
|
#define CPUPORT_H__
|
||
|
|
|
||
|
|
/* bytes of register width */
|
||
|
|
//#define ARCH_RISCV_FPU
|
||
|
|
#define ARCH_RISCV_FPU_S
|
||
|
|
|
||
|
|
#ifdef ARCH_CPU_64BIT
|
||
|
|
#define STORE sd
|
||
|
|
#define LOAD ld
|
||
|
|
#define REGBYTES 8
|
||
|
|
#else
|
||
|
|
#define STORE sw
|
||
|
|
#define LOAD lw
|
||
|
|
#define REGBYTES 4
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* FPU */
|
||
|
|
#ifdef ARCH_RISCV_FPU
|
||
|
|
#ifdef ARCH_RISCV_FPU_D
|
||
|
|
#define FSTORE fsd
|
||
|
|
#define FLOAD fld
|
||
|
|
#define FREGBYTES 8
|
||
|
|
#define rv_floatreg_t rt_int64_t
|
||
|
|
#endif
|
||
|
|
#ifdef ARCH_RISCV_FPU_S
|
||
|
|
#define FSTORE fsw
|
||
|
|
#define FLOAD flw
|
||
|
|
#define FREGBYTES 4
|
||
|
|
#define rv_floatreg_t rt_int32_t
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif
|